Patents Examined by Khamdan N. Alrobaie
  • Apparatus for calibrating sensing of memory cell data states
    Patent number: 11270774
    Abstract: Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
  • Single page read level tracking by bit error rate analysis
    Patent number: 11244732
    Abstract: A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
  • Apparatus for programming memory cells using multi-step programming pulses
    Patent number: 11238937
    Abstract: Memories having a controller configured to apply a particular multi-step programming pulse to a selected access line of a programming operation, enable for programming memory cells that have a particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a first threshold voltage level while applying a first step of a multi-step programming pulse to the selected access line, and enable for programming memory cells that have the particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a second threshold voltage level and higher than the first threshold voltage level while applying a second step of the multi-step programming pulse, lower than the first step of the multi-step programming pulse, to the selected access line.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Eric N. Lee
  • Mode-dependent heating of a memory device
    Patent number: 11238917
    Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Michael Dieter Richter, Martin Brox, Wolfgang Anton Spirkl, Thomas Hein
  • Reflow protection
    Patent number: 11222692
    Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sebastien Andre Jean, Ting Luo
  • Memory system
    Patent number: 11222703
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 11, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
  • Ferroelectric memory device
    Patent number: 11211108
    Abstract: The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 28, 2021
    Assignee: IMEC vzw
    Inventor: Jan Van Houdt
  • Passive compensation for electrical distance
    Patent number: 11205479
    Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John Fredric Schreck, Hari Giduturi
  • Memory architecture
    Patent number: 11164614
    Abstract: Systems and method are provided for a memory circuit. A predecoder circuit is configured to receive a first address signal, a first clock signal, and a second clock signal. The predecoder circuit is configured to generate a selection signal based on the first clock signal and the first address signal. And the predecoder circuit is further configured to maintain the selection signal based on the second clock signal and the first address signal.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Sanjeev Kumar Jain
  • Memory device with voltage boosting circuit
    Patent number: 11158360
    Abstract: A memory device including a voltage boosting circuit, a switching circuit and a word line driving circuit is provided. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is turned on or cut-off according to a first mode selection signal. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 26, 2021
    Assignee: DigWise Technology Corporation, LTD
    Inventors: Shih-Hao Chen, Wen-Pin Hsieh
  • Sram bit cell retention
    Patent number: 11152046
    Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 19, 2021
    Assignee: Apple Inc.
    Inventors: Jaroslav Raszka, Shahzad Nazar, Jaemyung Lim, Mohamed H. Abu-Rahma, Victor Zyuban
  • Differential sensing for a memory device
    Patent number: 11152049
    Abstract: Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Reduced retention leakage SRAM
    Patent number: 11145359
    Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 12, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ashish Kumar, Mohammad Aftab Alam
  • Method and system for reliable and secure memory erase
    Patent number: 11145368
    Abstract: A memory device has a switch matrix with a power supply input, a control input and a power supply output, a random access memory with a power supply connection coupled with the power supply output of the switch matrix. The switch matrix has a capacitor being chargeable by a power supply and upon receiving a control signal through the control input, the switch matrix is designed to decouple the capacitor from the power supply and the random access memory and to couple the capacitor through the power supply output with the random access memory in reverse polarity thereby providing a negative power supply to the power supply output.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Microchip Technology Incorporated
    Inventor: Ajay Kumar
  • Self-activated bias generator
    Patent number: 11139017
    Abstract: An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-An Chang, Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Yu-Der Chih
  • Memory operation with double-sided asymmetric decoders
    Patent number: 11139023
    Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technologhy, Inc.
    Inventors: Fabio Pellizzer, Nevil N. Gajera, John Frederic Schreck
  • 3D memory array clusters and resulting memory architecture
    Patent number: 11133049
    Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 28, 2021
    Assignee: TC Lab, Inc.
    Inventor: Bruce L. Bateman
  • Non-volatile semiconductor memory device and method for driving the same
    Patent number: 11133082
    Abstract: The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: September 28, 2021
    Assignee: Kioxia Corporation
    Inventor: Daisuke Uchida
  • Non-uniform state spacing in multi-state memory element for low-power operation
    Patent number: 11127458
    Abstract: A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 21, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Deepak Kamalanathan, Siddarth Krishnan, Fuxi Cai, Christophe J Chevallier
  • Page buffer and memory device including the same
    Patent number: 11114167
    Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se Won Yun, Kyung Min Kang, Dong Ku Kang