Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.

Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.

Abstract: A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.

Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.

Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

Abstract: Apparatuses and techniques are described for forming of selectors in a memory device such as a crosspoint memory array. A threshold switching selector is in series with a resistance-switching memory cell in a storage node. Prior to a first switching operation in the array, a stimulus is applied to the storage node to transform the selectors from an initial state having an initial threshold voltage to an operating state having a lower, operating threshold voltage. The stimulus can include a signal having a voltage which does not exceed the operating threshold voltage. To limit peak current consumption, the stimulus can be applied to different subsets of the array, one subset at a time.

Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Abstract: The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of memory blocks, the memory device configure to perform on each of the plurality of memory blocks at least one of a program operation, a read operation, or an erase operation in response to an internal command; and a controller in communication with a host and the memory device and configured to receive a request from the host and generate the internal command in response to the request from the host, the controller further configured to control the memory device to perform a stress check operation on a first memory block of the plurality of memory blocks in which the program operation has been completed.

Abstract: When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of (110) or (220), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of (110) or (220), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of (111).

Abstract: There may be provided a controller including an erase count monitor and a command generator. The erase count monitor may store and update an erase count value for the memory block. The erase count value may indicate a number of times an erase operation is performed for the memory block. The command generator may be configured to generate, based on the erase count value, a set command for setting a first select transistor among the select transistors to which an erase operation voltage is to be applied during the erase operation of the memory block, and a second select transistor among the select transistors to be floated when the erase operation voltage is to be applied to the first select transistor.

Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.

Abstract: Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.

Abstract: The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.