Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: repeatedly detecting whether a voltage supplied to the flash controller is lower than a first threshold; and issuing a program command to a flash module for programming data into the flash module and performing a supervision procedure when the voltage is lower than the first threshold. The supervision procedure includes steps for: repeatedly detecting whether the voltage is lower than a second threshold during a time period when issuing the program command to the flash module until transmitting the data to the flash module completely; and cancelling the program command when the voltage is lower than the second threshold.

Abstract: A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

Abstract: A semiconductor device includes: a first buffer circuit configured to receive a chip select signal in a power-down mode in response to a first select signal, a second buffer circuit configured to receive the chip select signal in an active mode in response to the first select signal, a power supply circuit configured to supply external power to a plurality of logic elements in the active mode in response to a second select signal, and not supply the external power to the plurality of logic elements in the power-down mode, and a select control circuit configured to transition a logic level of the second select signal at a first edge of a first chip select signal in the power-down mode, and then transition a logic level of the first select signal at a following second edge of the first chip select signal to exit from the power-down mode and enter the active mode.

Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

Abstract: A semiconductor device may include a sudden power detection circuit and an operation circuit. The sudden power detection circuit may generate a power-off control signal in a sudden power-off state. The operation circuit may discharge a specific node based on the power-off control signal.

Abstract: A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.

Abstract: A semiconductor apparatus including a sudden power detection circuit, a power-on reset circuit, and a driving circuit. The sudden power detection circuit configured to detect an external power supply voltage and generate a sudden power detection signal. The power-on reset circuit configured to detect the voltage level of the external power supply voltage according to a reset reference voltage and generate a power-on reset signal. The driving circuit configured to perform a sudden power-off operation and a power-on reset operation.

Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.

Abstract: A memory array including a plurality of memory cells and a plurality of drivers is disclosed. The plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. Memory cells corresponding to a row of the plurality of rows may be logically grouped into a plurality of memory array segments. The plurality of drivers may be coupled to corresponding first ends of corresponding memory array segments of the plurality of memory array segments. Second ends of the corresponding memory array segments may be coupled to second ends of corresponding adjacent memory array segments of the plurality of memory array segments. The second ends of the corresponding memory array segments and the second ends of corresponding adjacent memory array segments may be coupled to corresponding wordlines of a plurality of wordlines.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: A methodology and apparatus are disclosed for providing standby power during standby mode by applying a low frequency sampling clock signal to first and second comparators which are connected to compare an output voltage generated at an external capacitor to, respectively, a first higher voltage threshold and a second lower voltage threshold, where the first comparator generates an enable signal in response to the output voltage reaching the first higher voltage threshold for use in activating one or more switched regulator circuits to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold, and where the second comparator generates an undervoltage signal in response to the output voltage reaching the second lower voltage threshold for use in reactivating the main regulator to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold.

Abstract: A sub-wordline driver for a semiconductor memory device is disclosed. The sub-wordline driver includes a selection controller and a plurality of driving circuits. The selection controller selectively outputs any one of a first-group wordline selection signal and a second-group wordline selection signal in response to a selection signal and a wordline drive signal. The plurality of driving circuits selectively output any one of a plurality of sub-wordline drive signals in response to a main wordline drive signal, the wordline drive signal, the first-group wordline selection signal, and the second-group wordline selection signal.

Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

Abstract: Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterizing the quantum units and the couplers. The quantum Hamiltonian includes quantum annealer Hamiltonian and a quantum governor Hamiltonian. The quantum annealer Hamiltonian includes information bearing degrees of freedom. The quantum governor Hamiltonian includes non-information bearing degrees of freedom that are engineered to steer the dissipative dynamics of information bearing degrees of freedom.

Abstract: A neural network using a cross-point array is provided along with a pattern readout method thereof. Resistive memory devices are stacked vertically to form the neural network as synaptic devices. The connection strength of the signal passing between two neurons is controlled by the positive and negative conductance of the resistive memory devices and it is possible to recognize and readout patterns by learning in the cross-point array.

Abstract: The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized.

Abstract: Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.

Abstract: A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.