Abstract: A hard disk controller comprises a first circuit that transmits a first signal to control data transfer between the hard disk controller and a read/write channel. A second circuit transmits or receives data under control of the first signal. A third circuit transmits a second signal to control data transfer between a storage media and the read/write channel. A mode circuit transmits mode data under control of the second signal. A read channel circuit comprises a data circuit and a first circuit that receives a first signal that controls the transfer of data to and from the data circuit. A second circuit transmits or receives data under control of the first signal. A mode circuit receives mode data under control of a second signal. Data is transferred to and from the input/output circuit in accordance with the second signal.

Abstract: A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual I/O slots. The resource and partition manager uses the lock mechanism to obtain a lock on an I/O slot when transferring control of the I/O slot to a logical partition that is powering on and when removing the I/O slot from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of an I/O slot from, or return control to, an operating logical partition in order to facilitate hardware service operations on that I/O slot or on the physical enclosure in which it is contained.

Abstract: A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.

Abstract: A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an arbitration table. A priority is set to the packet data corresponding to a quantity of the packet data actually transferred on a serial communication path.

Abstract: A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.

Abstract: Methods, systems, and computer program products for transmitting first-priority data and second-priority data. The first-priority data and second-priority data are stored in separate data buffers, and the first-priority data is transmitted preferentially over the second-priority data.

Abstract: The invention relates to a slave bus subscriber for a serial data bus with a master bus subscriber, wherein the slave subscriber recognizes the bit rate of a data packet received over the data bus, whose header has a sync break field, a sync field and an ID field, with the help of the header of the data packet in such a manner that the periods between falling edges of bits having known bit intervals at least of the sync field and of the sync break field are evaluated and the bit rate is determined from the evaluated periods.

Abstract: A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history.

Abstract: A system and method for controlling memory operations is disclosed. In a particular embodiment, the system includes a memory controller that can request control of a contact that is shared between a first memory device and a second memory device. In a particular embodiment, the memory controller includes a state machine to request and receive control of the contact. In another particular embodiment, the first memory device is a non-volatile memory device and the second memory device is a volatile memory device.

Abstract: A buffer chip is used to isolate the internal connection between an HDMI receiver chip and a remotely-located HDMI port in a consumer electronic device. In one embodiment, an HDMI receiver/transmitter circuit is coupled to a main processor via an internal bus. The HDMI receiver/transmitter circuit, which includes one or more local HDMI inputs/outputs, is further electrically coupled to an HDMI buffer chip, which is in turn connected to one or more HDMI ports located remotely from the HDMI receiver/transmitter circuit. In one embodiment, the detection and control of the HDMI buffer chip is provided directly by the HDMI receiver/transmitter circuit. In another embodiment, the HDMI buffer chip may be electrically isolated from the device's main processor.

Abstract: A universal routing identifier (URID) is provided to extend the function space in PCI-Express fabrics. Methods and systems based on the URID are provided for configuring URID capable devices and upgrading PCI-Express bridges and switches having lookup tables with access control functionality. The lookup table entry contains URIDs of destination ports, backup ports, acceptance ports, and permitted ports for downstream and upstream filtering, routing and arbitrating of transaction packets. URID capable devices can be incrementally added to current PCI-Express bridges and switches. A configuration mechanism is added to the current PCI/PCI-Express enumeration software. The URID capabilities can be disabled to maintain system compatibility. A URID capable PCI-Express system is able to address ten of thousands single-function devices. A URID capability segment field is provided in the current PCI-Express configuration space.

Abstract: A bi-directional single conductor interrupt line is used in conjunction with a master only initiated data communication bus, to allow a slave device to submit a slave service request to a master device and to acknowledge master service requests from the master device. When not submitting a master service request, the master device maintains an interrupt line voltage at an idle state voltage by setting the interrupt line voltage through a pull resistor. The slave and master devices submit service requests by respectively driving or pulling the interrupt line voltage from the idle voltage to the service request voltage. The slave responds to a master service request or initiates the master servicing of a slave service request by subsequently driving the interrupt line back to the idle state voltage giving a slower slave ample time to prepare for a pending master initiated data transaction.

Abstract: A configuration space operation packet is received from a link. The configuration space operation packet is detected using a hardware mechanism. The configuration space operation packet is forwarded to a software-controlled entity for processing. A received packet can be detected as a configuration space operation packet from an address range of an address in a header of the received packet. The software-controlled entity can provide configuration space virtualisation.

Abstract: A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler.

Abstract: A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrupt may be based on the configuration of the module from which the interrupts are originated. In an embodiment of the present invention, the abstracted interrupt triggers an event. When the triggered event is completed, an interrupt may be fired off to the target module. An interrupt handler in the target module or an external interrupt handler may handle the interrupt that calls the target module.

Abstract: A technique for reducing information reception delays is provided. The technique reduces delays that may be caused by protocols that guarantee order and delivery, such as TCP/IP. The technique creates multiple connections between a sender and recipient computing devices and sends messages from the sender to the recipient on the multiple corrections redundantly. The recipient can then use the first arriving message and ignore the subsequently arriving redundant messages. The recipient can also wait for a period of time before determining which of the arrived messages to use. The technique may dynamically add connections if messages are not consistently received in a timely manner on multiple connections. Conversely, the technique may remove connections if messages are consistently received in a timely manner on multiple connections. The technique can accordingly be used with applications that are intolerant of data reception delays such as Voice over IP, real-time streaming audio, or real-time streaming video.

Abstract: A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.

Abstract: An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment.

Abstract: A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.

Abstract: Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.