Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.

Abstract: A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer.

Abstract: In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit.

Abstract: A detachable adapter is provided for being detachably connected to a data bus of a receptacle of a portable device to form a portable system. The adapter includes a conversion circuit and can inform the portable device that whether a power source is available and inform the portable device of connection status of the adapter through the data bus. The portable device can be connected to the power source through one of the receptacles of the adapter so that the portable device is powered or charged, and the portable device can be connected to at least one client device through the other receptacle of the adapter simultaneously.

Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: A virtual PCI Express device 1600 indicates the presence of a pseudo I/O device in a PCI Express initial configuration cycle to reserve a resource space for a device anticipated to be installed in the future, and when an I/O device 1400 is inserted into an unoccupied slot 1605, a virtual PCI Express device control logic 1602 notifies a downstream PCI-PCI bridge 1504 via a hot-plugging control line 1601, and the downstream PCI-PCI bridge 1504 generates an interrupt to a CPU 1100 to notify it of insertion of the I/O device 1400 in conformance with the procedure for hot plugging defined by the PCI-SIG Standards, and configuration software 1000 invoked configures the inserted I/O device 1400.

Abstract: The present invention relates to a data pipeline management system and more particularly to a minimum memory solution for unidirectional data pipeline management in a situation where both the Producer and Consumer need asynchronous access to the pipeline, data is non-atomic, and only the last complete (and validated) received message is relevant and once a data read from/write to the pipeline is initiated, that data must be completely processed. The data pipeline management system according to the invention can be implemented as a circular queue of as little as three entries and an additional handshake mechanism, implemented as a set of indices that can fit in a minimum of six bits (2×2+2×1). Both the Producer and Consumer will have a 2 bit index indicating where they are in the queue, and a 1 bit binary value indicating a special situation. Both parties can read all the indices but can only write their own, i.e. P and wrapP for the Producer and C and wrapC for the Consumer.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SATA and/or SAS standards and causing communication between one or more hosts and a SATA device. A multi-port bridge device is in communication with the one or more hosts through at least one link, the bridge device includes a power control block operative to control power to a SATA device through a power connection, wherein the power control block causes power to be provided to the SATA device even when the at least one link is operational.

Abstract: An interface (4) between a digital device (6) for transmitting and/or receiving a digital stream and a computer (2) comprises a digital stream transmitter/receiver (transceiver) (20), a computer bus interface (12) and a data converter (14, 16 & 18). The digital transceiver transmits digitally streamed content and/or receives digitally streamed content to/from the digital device. The computer bus interface receives/provides data to/from a computer bus of a computer for use by the computer and/or as provided by the computer. The data converter converts data received by the digital stream receiver into data useable by the computer from the computer bus and/or converts data received by the computer bus interface into digitally streamed data for transmission by the digital stream transmitter.

Abstract: Devices with multiple functions and methods for switching functions thereof are provided. The device comprises a plurality of hardware components, a plurality of functional modules, an input device, and a processing module. Each functional module corresponds to one of the functional connecting configurations for the hardware components. The processing module executes one of the functional modules and drives the hardware components according to the functional connecting configuration corresponding to the executed functional module. The processing module determines whether to generate a switch command according to an input command received by the input device. When the switch command is generated, the processing module directly terminates the functional module being currently executed and adjusts to execute another functional module, and drives the hardware components according to the functional connecting configuration corresponding to the functional module to be executed.

Abstract: Mechanisms for hot-plug/remove of a new component in a running communication fabric, such as a PCIe fabric, are provided. With these mechanisms, the addition of a new component in the fabric is detected and an event is sent to a multiple root fabric configuration manager. The multiple root fabric configuration manager gathers information about the new component and updates its I/O component tree structure in its configuration data structure to include the new component. The new component may then be utilized via the updated configuration data structure. When a component is to be removed, the multiple root fabric configuration manager receives an event indicating the component to be removed, determines which branches of the tree structure are affected by the removal, and updates its configuration data structure accordingly to remove the component and its associated components from the virtual plane of the removed component.

Abstract: A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 136 and a main memory 135 on the system bus 132 are retained in an associative memory 106 via an associative memory control unit 105. When an access to this data from an I/O device 138 on the local bus 137 is generated, the data are transferred from the associative memory 106 to the I/O device 138. Thus, when a data transfer request from the I/O device 138 to the main memory 135 is generated, no bus cycle is generated on the system bus 132 as long as this data are retained in the associative memory 106. Consequently, the data can be transferred at a high speed.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.

Abstract: An interrupt control apparatus that controls an interrupt process request caused by a predetermined interrupt factor is disclosed. The interrupt control apparatus includes: an obtaining unit configured to obtain an interrupt process request signal including an interrupt factor identifier associated with at least equal to or more than two interrupt factors; an interrupt process unit configured to execute an interrupt process requested by the interrupt process request signal; and a control unit configured to control the interrupt process unit so as not to execute interrupt processes caused by interrupt factors associated with the interrupt factor identifier until the interrupt process executed by the interrupt process unit ends.

Abstract: An interface supports a signaling protocol between a first hardware component and a second hardware component. The interface includes a first pin to provide a first clock signal sourced from the first hardware component to the second hardware component during a first operation, the first operation being an operation in which data is being transferred from the first hardware component to the second hardware component. A second pin to receive a second clock signal sourced from the second hardware component during a second operation, the second operation being an operation in which data is being transferred from the second hardware component to the first hardware component. A third pin to provide a first gate control signal sourced from the first hardware component to the second hardware component, the first gate control signal to synchronize data transfer between the first hardware component and the second hardware component during both the first operation and the second operation.

Abstract: Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.

Abstract: An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the network and analyzing device that analyzes identification data added to the data received by the receiving device. The apparatus also includes maintaining device which maintains a table that relates the identification data to information on identification of an interrupt register in each of the processors that execute the operating systems. The apparatus further includes interrupting device that allows interrupt processing to any of the processors to occur by writing the data received with the receiving device into the interrupt register that is related to the identification data, which is identified on the based of the table maintained by the maintaining device, analyzed by the analyzing device.

Abstract: Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.