Abstract: Requestors acquire tokens before issuing access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a first threshold, or in level 0, tokens are generated at a rate equivalent to 200% of a bus bandwidth. If the amount of accumulation is greater than the first threshold and is smaller than or equal to a second threshold, i.e., in level 1, tokens are generated at a rate equivalent to the bus bandwidth. If the amount of accumulation exceeds the second threshold, the token generation is stopped.

Abstract: A real-time industrial Ethernet EtherCAT system including a communication master and a plurality of slave nodes, wherein one slave node acts as a logic control master and the further slave nodes act as logic control slaves, and wherein a communication flow is as follows: the communication master sends a data fetching frame, when the data fetching frame passes through the logic control master, the logic control master inputs control data for the logic control slaves into the data fetching frame, when the data fetching frame passes through the logic control slaves, each logic control slave inputs status data into the data fetching frame, after return of the data fetching frame to the communication master, the communication master sends a data sending frame with output data, said output data being reorganized according to the control relationship between the logic control master and the logic control slaves by the communication master, when the data sending frame passes through the logic control master, the logi

Abstract: An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control block. The control block activates the second interface when a voltage level of a contact that the second host can be connected is in a first state at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivates the second interface when the voltage level of the contact is in a second state. The integrated circuit card has the integrated circuit built in.

Abstract: The present invention discloses a power saving method of a portable Internet device, the portable Internet device and its instant messaging system. If a screen of the portable Internet device is in non-view state, for example, both backlight module and LCD panel are turned off, it means that a user is not viewing the screen, and thus the message update frequency of the instant messaging program is lowered to prevent unnecessary transmission and receiving of wireless signals, so as to reduce power comsumption of the portable Internet device.

Abstract: System and method to configure switch systems are disclosed. A switch system includes leaf modules with internal ports and spine modules with ports. A midplane includes first layers closer to a first side, second layers closer to a second side and third layers between the first layers and the second layers. The midplane receives the leaf modules and the spine modules about both the first side and the second side. Conductors of the third layers couple internal ports of the leaf modules about one side to a port of spine modules about the other side. Conductors of the first layers couple internal ports of the leaf modules with ports of the spine modules about the first side. Conductors of the second layers couple internal ports of the leaf modules with ports of the spine modules about the second side.

Abstract: An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.

Abstract: A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.

Abstract: Provided are a cluster system, which can reduce power consumption by controlling power at a cluster level according to loads, and a power management method of the cluster system. The cluster system includes a plurality of management target nodes for performing an actual task which the cluster system is supposed to perform, a load balancer/switch for distributing a user's request received through an external network into the management target nodes, and a power management master for monitoring a load of an entire system and performing a power management by controlling the load balancer/switch. The power management master classifies the management target nodes into a power on group and a power off group.

Abstract: A system for improving dynamic response in a power supply includes a mainframe module having a memory and a mainframe microprocessor, the mainframe processor configured to calculate a plurality of tables in which each table represents a current/voltage (I/V) characteristic curve for the power supply, at least two power supply modules coupled to the mainframe module, each power supply module having a random access memory element, the random access memory element configured to receive and store a first table and a second table, wherein the mainframe microprocessor transfers the first table to each power supply module, and wherein each power supply module executes a respective first table while the mainframe processor calculates the second table for each power supply module and while the mainframe processor transfers the second table to each power supply module.

Abstract: A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 136 and a main memory 135 on the system bus 132 are retained in an associative memory 106 via an associative memory control unit 105. When an access to this data from an I/O device 138 on the local bus 137 is generated, the data are transferred from the associative memory 106 to the I/O device 138. Thus, when a data transfer request from the I/O device 138 to the main memory 135 is generated, no bus cycle is generated on the system bus 132 as long as this data are retained in the associative memory 106. Consequently, the data can be transferred at a high speed.

Abstract: A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flop of a next stage. A second D-type flip-flop receives one bit of enable control signal, and the output of each of the second D-type flip-flops connects to the input of a second D-type flip-flop of a next stage. A multiplexer contains two input terminals and an enable control signal receiving terminal, wherein one input terminal is used to receive the input data received by the first D-type flip-flop, and the enable control signal receiving terminal receives the enable control signal received by the second D-type flip-flop. A D-type latch outputs the data, and the output data is fed back to another input terminal of the multiplexer so as to be selected as a data output when a next set of data are input.

Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor package to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.

Abstract: Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device.

Abstract: The invention relates to a method for data transmission in a serial bus system comprising a control unit and bus users. The method comprises steps: receiving a first data telegram by a bus user from the control unit, wherein the data telegram has a data field containing output data; reading out the data field intended for the bus user from the first data telegram; preparing input data as a response to the read out data field; checking whether a predefined criterion is met, wherein if the criterion is met a second data telegram is newly generated and the input data is attached to the second data telegram and if the criterion is not met, the input data is attached to a data telegram previously received from another bus user; and transmitting the input data to the control unit by the second data telegram.

Abstract: A semiconductor device for detecting and compensating for a propagation delay of a tri-state bidirectional bus connected between a master block and a plurality of slave blocks. The master block controls the slave blocks. A bidirectional bus connects the master block and each of the slave blocks and accommodates transmission of data therebetween. A unidirectional bus is connected between the master block and each of the slave blocks. The unidirectional bus accommodates the transmission of control signals generated in the master block to the slave blocks wherein the master block detects a propagation delay time between the master block and the slave blocks. The master block counts the number of clocks from a time when a selected slave block transmits an allocated symbol to a time when the allocated symbol reaches the master block such that a propagation delay time between the master block and the selected slave block is detected and stored.

Abstract: A bus converter is disclosed that converts a signal of a synchronous bus into a signal of an asynchronous bus. The bus converter includes a control signal generation unit that generates n control signals synchronized at different timings of a predetermined synchronization signal, where n is an integer of two or more; and an output unit that outputs the signal of the synchronous bus divided into n signal groups based on a control using the n control signals.

Abstract: A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

Abstract: During an initial generation/assignment of location codes for field replaceable units (FRUs) that are and/or may be attached to the computer system, the service processor provides an alias location code for each FRU not currently attached. When the service processor later detects a concurrent install of the FRU, the service processor's firmware generates the correct location code from data retrieved from the FRU, and replaces the alias location code stored within the service processor's internal data structures with the correct location code. The firmware also forwards the correct location code back to a serviceability application, and the application utilizes the new location code in all remaining concurrent install commands to maintain a single, consistent view of the system.

Abstract: Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logical processor and a second logical processor associated with the at least one physical processor are partitioned. The first logical processor is assigned to manage interrupts and the second logical processor is assigned to dispatch runnable user threads.

Abstract: A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value.