Abstract: A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal.

Abstract: An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the chipset via a first PCI-Express I/F. A second controller controls communication with the engine when it is connected via a second PCI-Express I/F. A third controller controls communication with the engine when it is connected via a PCI I/F. The first controller receives, on behalf of the engine, an access from the CPU to the engine and inhibits a reference by the CPU to a resource connected to the image processing controller.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: A system and a method for determining a bus address for a controller within a network are provided. The method includes coupling a first set of pins of a wire harness connector to a second set of pins of a PCB connector of the controller. The method further includes sampling voltages of a portion of the first set of pins of the PCB connector to determine a wire harness ID utilizing a microprocessor. The method further includes accessing a look-up table from a memory device to select the bus address for the controller using the wire harness ID utilizing the microprocessor. The look-up table includes a plurality of bus addresses correspondingly associated with a plurality of wire harness IDs. The method further includes storing the selected bus address in the memory device utilizing the microprocessor.

Abstract: In one embodiment, the present invention includes a method for selecting first data received in a first die of a multi-chip package (MCP) from a second die of the MCP via an intra-package link for output from a selector during a first clock period of a first clock signal, selecting second data transmitted from the second die to the first die for output from the selector during a second clock period, and transmitting the first and second data from the MCP via an external link. Other embodiments are described and claimed.

Abstract: An integrated circuit having a plurality of data transceivers positioned on opposite ends of the integrated circuit is disclosed. The integrated circuit comprises a first plurality of data transceivers positioned in a column on a first end of the integrated circuit and a second plurality of data transceivers positioned in a column on a second end. A circuit is preferably positioned between the first plurality of data transceivers and the second plurality of data transceivers. The circuit could comprise, for example, circuits for implementing a programmable logic device. The circuitry of the plurality of data transceivers is also preferably arranged such that analog circuitry is positioned closer to an end of the integrated circuit than the digital circuits to reduce interference with the analog circuits. According to another aspect of the invention, the data transceivers are formed on layers to reduce the amount of interference.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: A computing system having a host device and at least one client device having a lock used to prevent modification of data in the client device. A lock clear signal from the host device causes the client device to clear a lock used to prevent modification of data stored in at least a protected portion of the client device where the client device remains fully operational.

Abstract: The invention discloses a general purpose interface controller, including a slave interface controller and a master interface controller, used to exchange data among master devices and slave devices in an electronic device. The slave interface controller receives data and a first control signal from one of the master devices, and converts the first control signal to a request signal. The master interface controller receives the data and the request signal from the slave interface controller, converts the request signal to a second control signal recognized by at least one of the slave devices, and forwards the data and the second control signal to the slave device.

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract: A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including processing power, memory and others that exceed the resources available on any single computer. A server agent program, a grid switch apparatus and a grid controller apparatus are included. Methods for creating processes and resources, and for accessing resources transparently across multiple servers are also provided.

Abstract: An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.

Abstract: A measurement or protective device has an interface for establishing a connection to at least one measurement transducer and a further interface for connecting to a superordinate data bus. In order to allow the measurement or protective device to be used in a particularly universal manner and to make it possible for complex protective systems to be constructed in a particularly cost-effective manner, a communication unit is provided in the measurement or protective device. The communication unit is connected to both interfaces, can be directly connected to the measurement transducer via the interface, can be connected to the superordinate data bus via the further interface, forms messages and transmits them to the superordinate data bus.

Abstract: In one embodiment, a method of managing critical resource usage in a storage network comprises receiving, in a storage controller, an input/output operation from a host, wherein the input/output operation identifies a storage unit, placing the input/output operation in a waiting queue, determining a maximum queue depth for at least one critical resource in the storage network required to execute the input/output command against the storage unit, and blocking one or more subsequent input/output commands from the host for the storage unit when the wait queue for the critical resource exceeds the maximum queue depth.

Abstract: A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction.

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

Abstract: A method for managing interruption of an out of box experience for an information handling system (IHS) whereby the method includes writing a flag to storage device, wherein the storage device is coupled to a processor within the IHS and executing an interruption handling sequence at the processor within the IHS, wherein the processor is operable to read the flag in the storage device as an input to the interruption handling sequence.

Abstract: There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.

Abstract: A smart docking system is provided by a portable electronic device that is adapted to dock with a media player shuttle. When docked, the media player shuttle adds the capability for rendering media content that is stored on the shuttle to the native functionality that is supported by the portable electronic device. The native functionality may vary, and may include that provided by a digital camera or handheld game device, for example. The media player shuttle includes storage for media content such as audio and video and a digital media processing system, but does not include a display screen or user controls. Instead, the display screen and user controls are provided by the portable electronic device when the shuttle is docked.

Abstract: A system for accessing a memory card is provided. The system includes a control unit having a control pin and a processor. The processor senses a card-insertion signal from a socket via the control pin for indicating whether the memory card has been inserted into the socket. The processor provides a power control signal via the control pin to supply an operating voltage to the memory card when the sensed card-insertion signal indicates that the memory card has been inserted into the socket. The processor detects whether a write protection function of the memory card is present via the control pin.