Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (?) from the output signal and the input signal. In various embodiments the extent to which the error signal (?) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal.

Abstract: An amplifying apparatus is provided. The amplifying apparatus comprises an amplifying circuit comprising a power amplifier and a bias circuit, the bias circuit is configured to detect an ambient temperature of the power amplifier to output a temperature voltage and regulate an internal current based on an input control signal to supply a bias current obtained by the regulation to the power amplifier; and a temperature control circuit that generates the control signal based on the temperature voltage during initial driving from a transmission mode starting point in time to an input point in time at which an input signal is input and outputting the control signal to the amplifying circuit.

Abstract: A vacuum tube amplification system includes: a first power circuit electrically connected to utility power alternating voltage to transform it into a first DC voltage; a first vacuum tube amplification load circuit having a first grounding end, the first vacuum tube amplification load circuit using the first DC voltage as operating voltage; a second power circuit electrically connected to the utility power alternating voltage to transform it into a second DC voltage and output the second DC voltage; and a second vacuum tube amplification load circuit having a second grounding end, the second vacuum tube amplification load circuit using the second DC voltage as operating voltage. The first grounding end is not directly electrically connected to the second grounding end, the first grounding end and the second grounding end are each electrically connected to a compliance ground of the utility power alternating voltage through a jumper-wire zero-ohm resistor.

Abstract: The present document discloses circuits and methods for providing an output voltage at an output port. In one of the embodiments, a circuit has a power amplifier having an output. In particular, the circuit may have a first transformer including a first coil and a second coil. Moreover, the circuit may have a first capacitor connected in parallel to the first coil and a second capacitor connected in parallel to the second coil. More particularly, the circuit may be adapted to have a first end of the first coil connected to the output of the power amplifier, and a second end of the first coil connected to the output port of the circuit.

Abstract: An amplifier includes a first input transistor, a second input transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal. The first current mirror circuit is coupled to the first input transistor and the second input transistor. The second current mirror circuit is coupled to the first input transistor, the second input transistor, and the first current mirror circuit.

Abstract: An audio device for reducing pop noise is adapted to compensate for a direct current (DC) offset of an audio source signal and output the audio source signal to an audio playing device. The audio device includes a linear operation circuit, an adder, a digital-to-analog circuit, and an amplification circuit. The digital-to-analog circuit is coupled between the adder and the amplification circuit. The linear operation circuit generates a DC offset value based on a linear equation, a temperature parameter, a slope parameter, and a constant. The adder is configured to process an input signal and the DC offset value to generate a calibration signal. The digital-to-analog circuit is configured to convert a calibration signal in a digital form to a calibration signal in an analog form. The amplification circuit is configured to process the calibration signal in the analog form to output the audio source signal.

Abstract: In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second amplifier input terminals and an amplifier output terminal integrally-formed with a semiconductor die, and at least two amplifier cells positioned adjacent to each other between the amplifier input terminals and the amplifier output terminal. Each amplifier cell includes first and second transistors (e.g., field effect transistors) integrally-formed with the semiconductor die, where the first and second transistors each include a transistor input (e.g., a gate terminal) and a transistor output (e.g., a drain terminal). The first transistor input is coupled to the first amplifier input terminal, and the second transistor input is coupled to the second amplifier input terminal. A combining node is coupled to the second transistor output and to the amplifier output terminal, and a first phase shift element (e.g., an inductor) is electrically connected between the first transistor output and the combining node.

Abstract: A Doherty amplifier system is disclosed. The Doherty amplifier system includes a carrier amplifier having a main input for receiving a first portion of a radio frequency (RF) signal and a main output in communication with a RF signal output. A peaking amplifier has a peak input for receiving a second portion of the RF signal and a peak output in communication with the RF signal output. Further included is a first impedance inverter coupled between the main output and the peak output. A second impedance inverter is coupled between the peak output and the RF signal output. A first impedance inverter coefficient of the first impedance inverter is numerically within ±10% of a second impedance inverter coefficient of the second impedance inverter.

Abstract: An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.

Abstract: A second main electrode of a first transistor is connected to a first main electrode of a sixth transistor, a second main electrode of the sixth transistor is connected to a first main electrode of a fifth transistor at a first node, a second main electrode of the fifth transistor is connected to a second main electrode of a second transistor, a control electrode of the fifth transistor is connected to the second main electrode of the fifth transistor, a second main electrode of a third transistor is connected to a first main electrode of a fourth transistor at a second node, and a control electrode of the fourth transistor is connected to the control electrode of the fifth transistor. A gain control amplifier controls a voltage supplied to a control electrode of the sixth transistor such that the first node and the second node are equal in voltage.

Abstract: A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.

Abstract: Embodiments are described herein for power generation systems and methods that use quadrature splitters and combiners to facilitate plasma stability and control. For one embodiment, a quadrature splitter receives an input signal and generates a first and second signals as outputs with the second signal being ninety degrees out of phase with respect to the first signal. Two amplifiers then generate a first and second amplified signals. A quadrature combiner receives the first and second amplified signals and generates a combined amplified signal that represents re-aligned versions of the first and second amplified signals. The power amplifiers can be combined into a system to generate a high power output to a processing chamber. Further, detectors can generate measurements used to monitor and control power generation. The power amplifiers, system, and methods provide significant advantages for high-power generation delivered to process chambers for plasma generation during plasma processing.

Abstract: A power amplifier circuit includes a power amplifier, first and second filters, and first and second output paths. The power amplifier is able to amplify both of a first signal and a second signal. The frequency of the second signal is higher than that of the first signal. The first filter includes a first inductor and attenuates the second signal amplified in the power amplifier. The first inductor serves as a path for the first signal amplified in the power amplifier. The second filter includes a first capacitor and attenuates the first signal amplified in the power amplifier. The first capacitor serves as a path for the second signal amplified in the power amplifier. The first signal outputted from the first filter is supplied to the first output path. The second signal outputted from the second filter is supplied to the second output path.

Abstract: An operational amplifier with totem pole connected output transistors having inputs coupled to multiplexers for selectable coupling of signals and voltage levels thereto. The high and low output transistors may be forced hard on or hard off in addition to normal coupling of signals thereto. The operation of the output transistors may be dynamically changed to pass only positive going signals, negative going signals, placed in a tristate high impedance state, hard connected to a supply voltage and/or hard connected to supply common return. A core independent peripheral (CIP) may also be coupled to the operational amplifier for dynamically changing the multiplexer inputs in real time, as can external control signals to a control circuit coupled to the multiplexers.

Abstract: Power amplifier (PA) devices and methods for fabricating PA devices containing inverted power transistor dies are disclosed. In embodiments, the PA device includes a first set of input and output leads, an inverted first power transistor (e.g., peaking) die electrically coupled between the first set of input and output leads, and a base flange. The inverted first power die includes, in turn, a die body having a die frontside and a die backside opposite the die frontside. A power transistor having a first contact region is formed in the die frontside. A frontside layer system is formed over the die frontside and the power transistor, while an electrically-conductive bond layer attaches the inverted first power transistor die to the base flange. The first contact region of the power transistor is electrically coupled to the base flange through the electrically-conductive bond layer and through the frontside layer system.

Abstract: An envelope tracking (ET) amplifier apparatus is provided. In examples discussed herein, the ET amplifier apparatus can be configured to operate in a fifth-generation (5G) standalone (SA) mode and a 5G non-standalone (NSA) mode. In the SA mode, the ET amplifier apparatus can enable a first pair of amplifier circuits to amplifier a 5G signal for concurrent transmission in a 5G band(s). In the NSA mode, the ET amplifier apparatus can enable a second pair of amplifier circuits to amplify a non-5G anchor signal and a 5G signal for concurrent transmission in a non-5G anchor band(s) and a 5G band(s), respectively. As such, the ET circuit may be provided in a communication apparatus (e.g., a 5G-enabled smartphone) to help improve power amplifier linearity and efficiency in both 5G SA and NSA modes.

Abstract: A digital amplifier that minimizes and restricts an analog signal system and uses a feedback signal and a dither signal is achieved. A pulse width modulator that adjusts a pulse width of a digital signal, a switching circuit that amplifies an output signal from the pulse width modulator, and a feedback signal generation unit that generates a feedback signal based on an output signal from the switching circuit are included, the pulse width modulator adjusts the pulse width of the digital signal with reference to the feedback signal, and the feedback signal generation unit includes a first amplifier that outputs a first amplified signal in which a difference between the output signal from the switching circuit and one of a reference voltage and a dither signal is amplified and a second amplifier that amplifies a difference between the first amplified signal and the other of the dither signal and the reference voltage and outputs the amplified difference as the feedback signal.

Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

Abstract: An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.