Abstract: A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

Abstract: A power detector has a signal input terminal, N limiting amplifiers, N rectifiers and a signal output terminal. N is an integer greater than 1. The signal input terminal receives an input signal, and the signal output terminal outputs a detection signal. The N limiting amplifiers generate N amplified signals according to N attenuated signals having different attenuation. Each limiting amplifier receives one of the N attenuated signals and outputs one of the N amplified signals. Each rectifier receives a corresponding amplified signal and outputs a rectified signal. The detection signal is associated with the sum of N rectified signals outputted from the N rectifiers, and all transistors of the power detector are bipolar junction transistors.

Abstract: In some implementations, there is provided an apparatus comprising a resonant amplifier circuit including a first inductor having a first inductive input and a first inductive output; a second inductor having a second inductive input and a second inductive output; a first switch coupled to the first inductive output; and a second switch coupled to the second inductive output, wherein the first switch and the second switched are driven out of phase, wherein the first inductor is configured to be resonant with a first capacitance associated with the first switch, and wherein the second inductor is configured to be resonant with a second capacitance associated with the second switch. Related systems and articles of manufacture are also provided.

Abstract: A low-power, low-noise amplifier with a negative feedback loop is provided. A low noise amplifier (LNA) includes a common gate (CG) amplifier, a common source (CS) amplifier having a gate connected to a source of the CG amplifier, a differential current balancer (DCB) connected to an output end of the CG amplifier and an output end of the CS amplifier, a symmetric load connected to the DCB, and a current bleeding circuit with one end connected to the output end of the CS amplifier and another end connected to the symmetric load, the current bleeding circuit including an active element and a load corresponding to the symmetric load, and an output end of the active element is connected to a gate of the CG amplifier.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-biased differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-biased differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Abstract: Disclosed are methods for biasing amplifiers and for manufacturing bias circuits bias for biasing amplifiers. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

Abstract: A signal amplifier device is provided to ensure the continuity of the gain of an amplifier. The signal amplifier device includes a main path and a sub path connected in parallel to the main path. A main path first amplifier circuit amplifies an input signal on the main path. A main path second amplifier circuit includes a common-gate transistor connected in series with an output of the main path first amplifier circuit without sharing a DC current. On the main sub path, the sub path amplifier circuit amplifies the input signal by using a gain lower than the maximum gain in the main path.

Abstract: In one embodiment, an RF power amplifier includes a first transistor and a second transistor in parallel, wherein a gate of the first transistor and a gate of the second transistor are configured to be driven by an RF source. A third transistor comprising a drain is operably coupled to both a source of the first transistor and a source of the second transistor. A control circuit is operably coupled to a gate of the third transistor and configured to alter a gate-to-source voltage of the third transistor, thereby altering a drain current of each of the first transistor and the second transistor, thereby altering an output power of the RF power amplifier.

Abstract: A differential amplifier includes: first and second input nodes; first and second output nodes; first and second supply nodes; first and second offset compensation nodes; first and second amplifier staged configured to generate first and second output voltages at the first and second output nodes as a function of first and second input voltages of the first and second input nodes and first and second offset compensation voltages of the first and second offset compensation nodes; and a feedback circuit configured to generate the first and second offset compensation voltages as a function of the first and the second output voltages. The feedback circuit includes: a coupling circuit coupled between the first and second offset compensation nodes, wherein the coupling circuit comprises one or more passive electric components.

Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases.

Abstract: A plurality of transmission lines (3b,3c) are connected to a transistor (1) and have different characteristic impedances. A plurality of open stubs (4a,4b) are connected to the plurality of transmission lines (3b,3c) respectively. A length of each open stub (4a,4b) is shorter than a length of each transmission line (3b,3c).

Abstract: The disclosed technology can include a power amplifier comprising an input, an output, and a transformer. The power amplifier can include a primary inductor coil coupled to the input, a secondary inductor coil coupled to the output, and three harmonic branches coupled to the primary coil. Each branch can comprise at least one electrical component having a tunable impedance.

Abstract: An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.

Abstract: A bias circuit includes a first branch circuit, a second branch circuit, a current amplifier and a switch, wherein the first branch circuit is configured to shunt an inputted first current, and input a first branch current of the first current to a power supply ground; the second branch circuit is configured to shunt the inputted first current, and input a second branch current of the first current to the current amplifier; the current amplifier is configured to receive the second branch current of the first current and amplify the second branch current of the first current to serve as a bias current of a power amplifier connected to the bias circuit for outputting; and the switch is configured to switch different resistance values for a resistor in the first branch circuit and/or switch different resistance values for a resistor in the second branch circuit.

Abstract: Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

Abstract: A power amplifier circuit includes a first transistor, a second transistor and a bias circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connecting to a collector of the first transistor and a collector configured to output a second signal. The bias circuit is coupled to the first transistor and the second transistor. The bias circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor about twice a DC voltage at the collector of the first transistor. The bias circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor about twice an AC or RF voltage at the collector of the first transistor.

Abstract: In a discrete supply modulation system, a circuit includes a multi-stage pulse shaping network (PSN) having a first PSN stage having an input configured to receive variable bias supply signals from a power management circuit (PMC) and having an output coupled to one or more second PSN stages with each of the one or more second PSN stages having an output configured to be coupled to a supply (or bias) terminal of a respective one of one or more radio frequency amplifiers. Such an arrangement is suitable for use with transmit systems in mobile handsets operating in accordance with 5th generation (5G) communications and other connectivity protocols such as 802.11 a/b/g/n/ac/ax/ad/ay and is suitable for use with multiple simultaneous transmit systems including multiple-input, multiple-output (MIMO), uplink carrier aggregation (ULCA) and beamforming.

Abstract: An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.

Abstract: Systems and methods are described for a power amplifier with a tracking power supply. The power amplifier may use envelope tracking. The power amplifier is protected when the output of the power amplifier is short circuited or overloaded.

Abstract: Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.