Abstract: A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.

Abstract: A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.

Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.

Abstract: A first module is configured to, based on an input sample, determine a first duty cycle. A second module is configured to, based on a battery voltage and the first duty cycle, determine a second duty cycle. A third module is configured to: set a scalar value based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage; and generate a start signal at a rate equal to a predetermined rate multiplied by the scalar value. A fourth module is configured to set a third duty cycle based on the second duty cycle and the scalar value. A fifth module is configured to generate a PWM output based on the start signal and the third duty cycle. A sixth module is configured to apply power to gates of FETs of a voltage converter based on the PWM output.

Abstract: A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals.

Abstract: A differential amplifier includes first and second MOS transistors of a first conductivity type which constitute a differential input circuit, a bias current source which supplies a bias current to the first and second MOS transistors, and a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and constituted to limit a back-gate voltage of the first and second MOS transistors.

Abstract: An amplifier circuit structure can include an amplifier located in a main path, and a first switch located in a bypass. One end of a second switch is a signal output end of the amplifier circuit structure, and the other end of the second switch is configured to selectively connect to a signal output end of the bypass or a signal output end of the main path. The first and second switches are configured to control their respective operating states when a first instruction is received, such that the main path is connected to the signal input end and the signal output end of the amplifier circuit structure; and to control their respective operating states when a second instruction is received, such that the bypass is connected to the signal input end of the amplifier circuit structure and the signal output end of the amplifier circuit structure.

Abstract: An object is to provide a method and a system of adjusting a power amplifier which makes it possible to adjust a linearizer using signals of two carriers by the same power, to reduce the influence of the non-linearity on a multicarrier signal compared with the conventional. A method of adjusting a power amplifier, the power amplifier including a linearizer to reduce an intermodulation caused by non-linearity of the power amplifier, includes: inputting two signals generated by a signal generator into the power amplifier; measuring power of each order of first intermodulations of the two signals output from the power amplifier; calculating a power sum of second intermodulations by the plurality of signals using the measured power of each order of the first intermodulations; and adjusting the linearizer so that the power sum of the second intermodulations by the plurality of signals takes a minimum value or at most a predetermined value.

Abstract: Example embodiments relate to amplifiers having improved stability.

Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.

Abstract: An amplifier comprises: an input stage, a pulse width modulation stage, and a switched output stage. During operation, the input stage receives an input signal (such as an audio signal). The input stage adjusts the input signal based on feedback from the switched output stage of the amplifier. According to one configuration, the feedback from the switched output stage is a voltage across a flying capacitor disposed in the switched output stage. The pulse width modulation stage uses the adjusted input signal or signals to produce respective pulse width modulation signals that are subsequently used to drive (control) switches in the switched output stage. The switches in the switched output stage generate an output voltage to drive a load based on states of the pulse width modulation signals. Adjustments applied to the input signal based on the feedback maintains the magnitude of the flying capacitor voltage at a desired setpoint.

Abstract: A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.

Abstract: Systems, methods and apparatus for wireless charging are disclosed. A charging apparatus has an amplifier stage, a power switching stage and a controller. The amplifier stage has a choke that receives a current from an input of the amplifier stage, a resonant network coupled to an output of the choke and that provides an output current to a load, and a first switch configured to short the output of the choke to circuit ground when turned on. The power switching stage may be configured to couple a power supply to the input of the amplifier stage and may have a second switch operable to couple the input of the amplifier stage to circuit ground when turned on. The controller may be configured to control operation of the first switch and the second switch in accordance with a timing sequence that defines a cycle of the output current.

Abstract: A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

Abstract: An electrical system includes a power supply and an electrical circuit coupled to the power supply and including an operational amplifier. The operational amplifier includes an input stage and a pre-driver stage coupled to the input stage, wherein the pre-driver stage includes a first input terminal, a second input terminal, and a voltage supply terminal. The operational amplifier also includes an output stage with bipolar transistors coupled to the pre-driver stage. The pre-driver stage is configured to: detect a voltage differential across the first and second input terminals of the pre-driver stage; and provide an adjustable bias current based on the voltage differential.

Abstract: A radio frequency circuit includes a power amplifier configured to selectively amplify one of a first radio frequency signal and a second radio frequency signal that have different bandwidths, and when the first radio frequency signal is input to the power amplifier, a first bias signal is applied to the power amplifier, and when the second radio frequency signal is input to the power amplifier, a second bias signal different from the first bias signal is applied to the power amplifier.

Abstract: This application is generally related to methods and systems for improving amplifier performance. For example, the system includes two or more gain and phase modulators. The system also includes two or more component amplifiers operably coupled to, and downstream of, the power splitter, where each of the two or more component amplifiers is operably coupled to a respective one of the two or more gain and phase modulators. The system further includes a power combiner operably coupled to, and downstream of, the two or more component amplifiers, configured to output a power signal. The system even further includes a Walsh generator configured to generate and transmit first and second Walsh codes to each of the two or more gain and phase modulators. The first Walsh code is orthogonal to the second Walsh code. A first set of the first and second Walsh codes is inverted with respect to a second set of the first and second Walsh codes.

Abstract: In some embodiments, a circuit includes: a first chopping circuit configured to receive an input signal and generate a modulated signal responsive to the input signal; first and second input capacitors selectively coupled to receive a modulated signal or a common-mode voltage; an amplifier having an input and an output, the input coupled to the first and second input capacitors; an auto-zeroing circuit comprising one or more auto-zeroing feedback capacitors selectively coupled between the amplifier input and output; a gain selection circuit comprising one or more gain selection feedback capacitors coupled to the amplifier input and selectively coupled to the amplifier output or the common-mode voltage; an offset compensation circuit comprising one or more offset capacitors coupled to the amplifier input and selectively coupled to a reference voltage or the common-mode voltage; and a second chopping circuit configured to generate a demodulated signal responsive to the amplifier output.

Abstract: The present invention provides a feedback system including a mixing circuit, a forward circuit, a feedback circuit, a feedback gain circuit and a control circuit. In the operations of the feedback system, the mixing circuit generates a mixed signal according to an input signal and a feedback signal, the forward circuit processes the mixed signal to generate an output signal, the feedback gain circuit and the feedback circuit generates the feedback signal according to the output signal, and the control circuit determines a feedback gain of the feedback gain circuit according to a gain of the forward circuit.

Abstract: An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.