Abstract: A multilayered bottom electrode for a magnetic tunnel junction (MTJ) containing device is provided that includes, from bottom to top, a base segment having a first diameter and composed of a remaining portion of a first bottom electrode metal-containing layer, a middle segment having a second diameter and composed of a remaining portion of a second bottom electrode metal-containing layer, and an upper segment having a third diameter and composed of a remaining portion of a third bottom electrode metal-containing layer, wherein the first diameter is greater than the second diameter, and the third diameter is equal to, or less than, the second diameter. The wider base segment of each multilayered bottom electrode prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.

Abstract: An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.

Abstract: A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.

Abstract: A bias timing control circuit includes a current source, a bias switch circuit, a duty cycle sensing circuit, and a switching control circuit. The bias switch circuit includes a first path switch, connected between an output node of the current source and a bias amplifying circuit, and a second path switch, connected between the output node of the current source and a temperature compensation circuit. The duty cycle sensing circuit is configured to generate a timing control signal based on a duty cycle of a transmission enable signal. The switching control circuit is configured to control a first turn-on time of the first path switch during an initial startup period, and a second turn-on time of the second path switch during a normal driving period subsequent to the initial startup period to adjust a warm-up time of a power amplifying circuit based on the timing control signal.

Abstract: Embodiments of the present invention are directed to a method and apparatus for operating a gaming device having at least one winning event and at least one related award that is generated according to a set of rules associated with the game. The game is driven to present a predefined winning outcome and an award is generated as if the winning event and award were generated according to the rules. Also provided are rules and/or conditions for determining when to generate the predefined wining event, including rules that take into account player value to the casino and game volatility preference.

Abstract: An optoelectronic component may include at least one semiconductor chip for emitting electromagnetic radiation, a conversion element, and an optical element. The conversion element may at least partially convert primary radiation emitted by the semiconductor chip(s) into secondary radiation where the conversion element is arranged downstream of the semiconductor chip(s) in the emission direction and is arranged on the semiconductor chip(s). The optical element may be arranged downstream of the conversion element in the emission direction and where the conversion element is subdivided into individual portions.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.

Abstract: IGBT semiconductor structure having a p+ substrate, an n? layer, at least one p region adjacent to the n? layer, and at least one n+ region adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the n? layer, and the n+ region forms a second p-n junction together with the at least one p region. The dielectric layer covers the first p-n junction and the second p-n junction. The second terminal contact is implemented as a field plate on the dielectric layer and a doped intermediate layer with a layer thickness of 1 ?m-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the p+ substrate and the n? layer, wherein the intermediate layer is integrally joined to at least the p+ substrate.

Abstract: Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.

Abstract: Radio frequency amplifiers with overload protection are provided herein. In certain configurations, an RF amplifier system includes an RF amplifier that receives an RF signal from an input terminal and that generates an amplified RF signal at an output terminal, and an overload detection circuit that generates a detection signal indicating a detected signal level of the RF amplifier. The RF amplifier includes an amplification device that amplifies the RF signal and a degeneration circuit that provides degeneration to the amplification device. Additionally, the detection signal is operable to control an amount of degeneration provided by the degeneration circuit so as to protect the RF amplifier from overload.

Abstract: An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input.

Abstract: The technology described in this document can be embodied in an audio power amplifier that includes a first channel and a second channel. Each of the first channel and the second channel includes an input to receive an input signal, a pair of switching devices, drive circuitry for driving the pair of switching devices to produce a signal, and an output filter to filter the signal from the pair of switching devices. The output filter is configured to provide the filtered signal to an audio load. Each of the first channel and the second channel includes a voltage feedback loop to provide a voltage of the filtered signal to a voltage controller of the audio power amplifier, and a current feedback loop to provide a current of the filtered signal to a current controller of the audio power amplifier. The audio power amplifier includes a summer for combining the input of the first channel and the input of the second channel when an output of the first channel is connected to an output of the second channel.

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

Abstract: A Doherty amplifier is disclosed with a main amplifier having a main input in communication with a radio frequency (RF) signal input and a main output in communication with a RF signal output. Also included is a peaking amplifier having a peak input in communication with the RF signal input and a peak output in communication with the RF signal input. Further included is main neutralization circuitry having a main neutralization input in communication with the peak input and a main neutralization output in communication with the main input, wherein the main neutralization circuitry is configured to inject a main neutralization signal into the main input such that the main neutralization signal is 180°±10% out of phase and equal in amplitude to within ±10% of a main parasitic feedback signal passed from the main output to the main input by way of a main parasitic feedback capacitance.

Abstract: The formation of solar cell contacts using a laser is described. A method of fabricating a back-contact solar cell includes forming a poly-crystalline material layer above a single-crystalline substrate. The method also includes forming a dielectric material stack above the poly-crystalline material layer. The method also includes forming, by laser ablation, a plurality of contacts holes in the dielectric material stack, each of the contact holes exposing a portion of the poly-crystalline material layer; and forming conductive contacts in the plurality of contact holes.

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Abstract: A package includes a semiconductor die having a first load terminal at a first side and a second load terminal at a second side opposite the first side, a metal block attached to the second load terminal and providing a single primary thermal conduction path of the package, a first metal lead electrically connected to the first load terminal, a second metal lead electrically connected to the second load terminal, and a mold compound embedding the semiconductor die, the metal block, and each metal lead. Each metal lead and the metal block are exposed from the mold compound at a first side of the package. Each metal lead is exposed from the mold compound at a second side of the package opposite the first side, so that the package is configured for surface mounting at either the first side or the second side of the package.

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

Abstract: A semiconductor device includes a compound semiconductor layer disposed over a substrate, a protection layer disposed over the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode which penetrate through the protection layer and are disposed on the compound semiconductor layer. The semiconductor device also includes a gate field plate connecting the gate electrode and disposed over a portion of the protection layer between the gate electrode and the drain electrode. The gate field plate has an extension portion extending into the protection layer.