Patents Examined by Khiem D Nguyen
  • Semiconductor package including a first sub-package stacked atop a second sub-package
    Patent number: 11239217
    Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Amplifier
    Patent number: 11232937
    Abstract: A capacitive trans-impedance amplifier comprising a voltage amplifier having an inverting input terminal for connection to an input current source. A feed-back capacitor is coupled between the inverting input terminal and the output terminal to accumulate charges received from the input current source and to generate a feed-back voltage accordingly. A calibration unit includes a calibration capacitor electrically coupled, via a calibration switch, to the inverting input terminal and electrically coupled to the feed-back capacitor. The calibration unit is operable to switch the calibration switch to a calibration state permitting a discharge of a quantity of charge from the calibration capacitor to the feed-back capacitor.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 25, 2022
    Assignee: ISOTOPX LTD
    Inventors: Vadim Volkovoy, Anthony Michael Jones, Damian Paul Tootell
  • Distortion imparting device and distortion imparting method
    Patent number: 11233491
    Abstract: A distortion imparting device capable of obtaining a natural distortion effect even when output is decreased is provided. The distortion imparting device includes a first amplification part which attenuates an input audio signal on the basis of an attenuation factor set by a user and amplifies the attenuated audio signal, a second amplification part serially connected to the first amplification part, and a limiting part which is connected between an output terminal of the first amplification part and an input terminal of the second amplification part and limits an input voltage of the second amplification part to a predetermined clip voltage, wherein the limiting part determines the clip voltage on the basis of the attenuation factor.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: January 25, 2022
    Assignee: Roland Corporation
    Inventors: Mitsuo Shida, Toshiyuki Ochi, Yoshinobu Morimoto, Kosuke Takada
  • Amplifier and receiving circuit, semiconductor apparatus, and semiconductor system using the same
    Patent number: 11233489
    Abstract: An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Transistor having at least one transistor cell with a field electrode
    Patent number: 11227945
    Abstract: A transistor device includes at least one transistor cell which includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode. A portion of the semiconductor body is arranged between the field electrode trench and the first surface of the semiconductor body. The portion of the semiconductor body that is arranged between the field electrode trench and the first surface comprises the body region. The body region directly contacts the upper surface of the field electrode dielectric.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: January 18, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler
  • Method of manufacturing an LED carrier assembly having an embedded alignment magnet
    Patent number: 11227853
    Abstract: The invention describes a method of manufacturing an LED carrier assembly, which method comprises the steps of providing a carrier comprising a mounting surface with mounting pads arranged to receive a number of LED dies; embedding an alignment magnet in the carrier; providing a number of LED dies, wherein an LED die comprises a number of magnetic die pads; and aligning the magnetic die pads to the mounting pads by arranging the LED dies over the mounting surface of the carrier within magnetic range of the alignment magnet. The invention also describes an LED carrier assembly.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 18, 2022
    Assignee: Lumileds LLC
    Inventors: Casey Israel, Florent Monestier, Benno Spinger
  • Apparatus and method for calibrating characteristics of power amplifier in transmitter
    Patent number: 11228281
    Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 18, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hsien Chang, Yu-Ming Lai, Ching-Chia Cheng, Wei-Kai Hong, Yi-Chu Chen, Tsung-Ming Chen, Shih-Chieh Yen
  • Semiconductor wafer processing arrangement employing an adhesive sheet and method for processing a semiconductor wafer
    Patent number: 11222864
    Abstract: A semiconductor wafer support arrangement and method for processing a semiconductor wafer including an adhesive sheet may comprise: a layer of wafer supporting adhesive that has certain characteristics that permit wafer processing, e.g., wafer thinning, and removal of the processed wafer in condition for use without cleaning. The carrier or substrate for the wafer processing may be reusable, and the adhesive sheet may have plural layers and may include a flexible substrate.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 11, 2022
    Assignee: Amerasia International Technology
    Inventors: Kevin Kwong-Tai Chung, Frederick Lo
  • Edge termination designs for super junction device
    Patent number: 11222962
    Abstract: This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of doped columns of a second conductivity type. The termination area further comprises a plurality of surface guard ring regions of the second conductivity type dispose near a top surface of the epitaxial layer close to the doped columns of the second conductivity type. In one of the embodiments, one of the surface guard ring regions extending laterally over several of the doped columns in the termination area.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 11, 2022
    Assignee: HUNTECK SEMICONDUCTOR (SHANGHAI) CO. LTD.
    Inventor: Jun Hu
  • Image sensor device having first lens over a light-sensing region and surrounded by a grid layer
    Patent number: 11222913
    Abstract: An image sensor device is provided. The image sensor device includes a substrate. The image sensor device includes a light-sensing region in the substrate. The image sensor device includes an isolation structure in the substrate. The isolation structure surrounds the light-sensing region. The image sensor device includes a grid layer over the substrate. The grid layer is over the isolation structure. The image sensor device includes a first lens over the light-sensing region and surrounded by the grid layer. The image sensor device includes a color filter layer over and in direct contact with the first lens. The image sensor device includes a second lens over the color filter layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Hsun Hsu
  • Aligning bumps in fan-out packaging process
    Patent number: 11217555
    Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Epitaxial fin structures having an epitaxial buffer region and an epitaxial capping region
    Patent number: 11211473
    Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li
  • Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices
    Patent number: 11210447
    Abstract: The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. A second type of semiconductor device includes: a second fin structure extending in a third direction, a second gate, and a second slot contact disposed over the second fin structure. The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is greater than the second gate dimension and greater than the first slot contact dimension.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiefeng Jeff Lin, Chih-Yung Lin, Dian-Sheg Yu, Hsiao-Lan Yang, Jhon Jhy Liaw
  • Wiring structure having at least one sub-unit
    Patent number: 11211299
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Temperature compensation circuit and temperature compensated amplifier circuit
    Patent number: 11196391
    Abstract: Embodiments of a temperature compensation circuit and a temperature compensated amplifier circuit are disclosed. In an embodiment, a temperature compensation circuit includes a bias reference circuit having serially connected transistor devices and a driver transistor device connected to the bias reference circuit. At least one of the serially connected transistor devices includes a resistor connected between two terminals of the at least one of the serially connected transistor devices. The driver transistor device is configured to generate a drive current based on a resistance value of the resistor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Joseph Staudinger, Yu You, Donald Vernon Hayes
  • Systems and methods for operating a bias controller for an amplifier circuit
    Patent number: 11194357
    Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a bias controller for an amplifier circuit involves obtaining temperature data corresponding to a temperature of the amplifier circuit, generating a proportional to absolute temperature (PTAT) bias voltage based on a first PTAT slope when the temperature is within a first range of temperatures or a second PTAT slope when the temperature is within a second range of temperatures, wherein the second PTAT slope is greater than the first PTAT slope, and biasing the amplifier circuit based on the generated PTAT bias voltage.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Xu Jason Ma, Ngai-Ming Lau
  • Memory device and electronic device including insulating patterns with different thermal conductivities
    Patent number: 11189630
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Gun Kang, Hyun Seok Kang, Deok Lae Ahn, Jae Geun Oh, Won Ki Joo, Su-Jin Chae
  • Valley detection for supply voltage modulation in power amplifier circuits
    Patent number: 11190141
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Multilayered bottom electrode for MTJ-containing devices
    Patent number: 11189782
    Abstract: A multilayered bottom electrode for a magnetic tunnel junction (MTJ) containing device is provided that includes, from bottom to top, a base segment having a first diameter and composed of a remaining portion of a first bottom electrode metal-containing layer, a middle segment having a second diameter and composed of a remaining portion of a second bottom electrode metal-containing layer, and an upper segment having a third diameter and composed of a remaining portion of a third bottom electrode metal-containing layer, wherein the first diameter is greater than the second diameter, and the third diameter is equal to, or less than, the second diameter. The wider base segment of each multilayered bottom electrode prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Thitima Suwannasiri, Nathan P. Marchack, Pouya Hashemi
  • Low-noise amplifier with quantized conduction channel
    Patent number: 11183978
    Abstract: An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Cezar Bogdan Zota, Lukas Czornomaz