Abstract: A semiconductor structure includes a first substrate, a second substrate, a metal layer, a buffer structure, and a barrier structure. The first substrate has a landing pad. The second substrate is disposed over the first substrate. The metal layer is disposed in the second substrate and extends from the landing pad to a top surface of the second substrate. The buffer structure is disposed in the second substrate and surrounded by the metal layer, in which a top surface of the buffer structure is below a top surface of the metal layer. The barrier structure is disposed over the metal layer and the buffer structure.

Abstract: An envelope tracking (ET) amplifier apparatus is provided. The ET amplifier apparatus includes a distributed ET integrated circuit (DETIC) configured to generate a distributed ET voltage. The DETIC may be coupled to a higher-bandwidth (HB) amplifier circuit and a lower-bandwidth (LB) amplifier circuit configured to amplify an HB radio frequency (RF) signal and an LB RF signal, respectively. In examples discussed herein, the DETIC may be configured to selectively provide the ET voltage to one of the HB amplifier circuit and the LB amplifier circuit, depending on which of the HB amplifier circuit and the LB amplifier circuit is activated. By providing the DETIC in proximity to the HB amplifier circuit and the LB amplifier circuit, it may be possible to reduce potential distortion to the HB RF signal and the LB RF signal, without significantly increasing footprint of the ET amplifier apparatus.

Abstract: A distributed networking system and protocol is provided to a networking system with a modular design. The distributed networking system may include a networking system, modules, control module, user interface module, input/output module, network module, data transmission network, hybrid modules and composite modules. A method to interface with accessories of a system with a modular design using the distributed networking system and protocol is also provided.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

Abstract: A chip package structure and a chip package method, the chip package structure including a die and a package substrate disposed around the die. A solder joint is disposed on a first surface of the die. Remaining surfaces of the die other than a second surface are wrapped by an injection molding material. At least one pair of opposite sides of the package substrate is embedded in the injection molding material. A contact area between the pair of opposite sides and the injection molding material accounts for more than half of a surface area of the pair of opposite sides. The second surface is a surface that is of the die and that is opposite to the first surface.

Abstract: It is configured to output a first I signal having passed through a first inverse characteristic circuit having inverse frequency characteristics to frequency characteristics of a first loop filter circuit, to the first loop filter circuit, and output a first Q signal having passed through a second inverse characteristic circuit having inverse frequency characteristics to frequency characteristics of a second loop filter circuit, to the second loop filter circuit.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes: a gate stack structure including interlayer insulating layers and conductive patterns stacked in a first direction; a channel structure penetrating the gate stack structure; a peripheral contact plug spaced apart from the gate stack structure on a plane intersecting the channel structure, the peripheral contact plug extending in the first direction; and a capacitor spaced apart from the gate stack structure and the peripheral contact plug on the plane, the capacitor having an area wider than an area of the peripheral contact plug.

Abstract: An integrated device package is disclosed. The integrated device package can include a substrate that has an upper side and a lower side opposite the upper side. The integrated device package can include an integrated device die that is mounted to the lower side of the substrate. The integrated device die has a first side facing the lower side of the substrate and a second side opposite the first side. The package can include a molding material in which the integrated device die is at least partially embedded. The package can include a thermally conductive element coupled to the second side of the integrated device die. At least a portion of the thermally conductive element can be exposed through the molding material. The thermally conductive element can be a heat sink. The package can include an interconnect that is configured to provide an external connection. The interconnect extends at least partially through the molding material from the lower side of the substrate.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: The present general inventive concept is directed to a method and system to generate a power signal, including summing a non-inverted reference signal and an inverted feedback signal to output a non-inverted first summation signal, summing an inverted reference signal and a non-inverted feedback signal to output an inverted second summation signal, receiving the first summation signal at a non-inverted input of a differential power output driver, and the second summation signal at an inverted input of the differential power output driver, outputting a non-inverted power signal to a first terminal of an impedance load from a non-inverted output of the differential power output driver, and outputting an inverted power signal to a second terminal of the load from an inverted output of the differential power output driver, the non-inverted power signal also being used as the non-inverted feedback signal, and the inverted power signal also being used as the inverted feedback signal.

Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Abstract: An amplification circuit includes a filter circuit, an amplifier, a capacitor, a bypass line, and a switch circuit that includes a first FET and a second FET connected in series between one end and the other end of the bypass line, a first resistance element connected in series to a gate of the first FET, and a second resistance element connected in series to a gate of the second FET. A first control signal is supplied to the gate of the first FET. A second control signal is supplied to the gate of the second FET. A product of a gate length and a gate width of the first FET and a resistance value of the first resistance element is smaller than a product of a gate length and a gate width of the second FET and a resistance value of the second resistance element.

Abstract: A method comprises: measuring reflected and forward power at a power amplifier output; determining if the reflected power equals to or exceeds a first level; if the reflected power is equal to or exceeds the first level, then reduce power of a power amplifier input signal; determining if a standing wave ratio at the power amplifier output equals or exceeds a second level; if the standing wave ratio at the power amplifier output equals or exceeds the second level, then reducing the power amplifier input signal power level and/or sending an alarm; determining if the power amplifier output power equals or exceeds a third level; and if the power output from the power amplifier equals or exceeds the third level, then reducing the power amplifier input signal power level until such power level is less than or equal to the third level and/or sending an alarm.

Abstract: In some embodiments, a power amplification system can comprise a current source, an input switch configured to alternatively feed current from the current source to a high-power circuit path and a low-power circuit path, and a band switch including a switch arm for switching between a plurality of bands. Each of the high-power circuit path and the low-power circuit path can be connected to the switch arm.

Abstract: A semiconductor device of embodiments includes a substrate; a semiconductor chip provided above the substrate; a first ultrasonic bonding portion provided between the substrate and the semiconductor chip; a first terminal plate electrically connected to the semiconductor chip via the first ultrasonic bonding portion, the first ultrasonic bonding portion being provided on the substrate, and the first terminal plate having a first surface facing the semiconductor chip; and a first adhesive layer provided on the first surface, and the first adhesive layer containing a first adhesive.

Abstract: A semiconductor device disclosed in an embodiment comprises: a light emitting unit comprising a light emitting structure layer which has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a sensor unit disposed on the light emitting unit, wherein the sensor unit comprises: a sensing material changing in resistance with light emitted by the light emitting unit; a first sensor electrode comprising a first pad portion and a first extension part extending from the first pad portion and contacting the sensing material; and a second sensor electrode comprising a first pad portion and a second extension part extending toward the first extension part from the second pad portion and contacting the sensing material. The sensor unit senses an external gas in response to the light generated from the light emitting unit.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions.

Abstract: Embodiments of the present application relate to the field of ground detection, and disclose a ground detection device, a robot and a ground detection method. The ground detection device includes a control circuit, a signal trigger circuit, a signal sampling circuit and an amplification circuit. Where, the signal sampling circuit is configured to acquire reflected light of the optical signal reflected by a detection area and ambient interference light, and to generate a second voltage signal according to the reflected light and the ambient interference light; the amplification circuit is configured to amplify the second voltage signal to acquire a third voltage signal; and the control circuit is configured to compare the third voltage signal with a preset voltage, and to determine whether there is a ground within the detection area according to a comparison result.

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.