Patents Examined by Kim T. Huynh
  • Patent number: 11900150
    Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 13, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chih-Hsiang Hsu, Wei-Wei Li, Shang-Lin Tsai, Lueh-Chih Fang
  • Patent number: 11886372
    Abstract: The present disclosure relates to packing transaction layer (TL) packets at a link layer of a protocol stack. In some examples, channel type data identify a type of message channel for a first TL packet can be generated. A set of slot formats for a slot for packing the first TL packet can be identified based on the channel type data and a slot format database. A respective slot format of the set of slot formats can be selected for the slot based on a message type of the first TL packet, and a message type of a second TL packet. The first TL packet and the second TL packet can be packed into the slot having the selected respective slot format during generation of a link layer packet.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 30, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Claire Liyan Ying, Uyen Huynh Ha Nguyen, Shu Wang
  • Patent number: 11882025
    Abstract: A network interface controller (NIC) capable of performing message passing interface (MPI) list matching is provided. The NIC can include a host interface, a network interface, and a hardware list-processing engine (LPE). The host interface can couple the NIC to a host device. The network interface can couple the NIC to a network. During operation, the LPE can receive a match request and perform MPI list matching based on the received match request.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: January 23, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Partha Pratim Kundu, Andrew S. Kopser, Duncan Roweth, Robert Alverson
  • Patent number: 11875839
    Abstract: Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Ben-Zion Friedman, Eliezer Tamir, Manasi Deval
  • Patent number: 11868296
    Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Gregory K. Chen
  • Patent number: 11853179
    Abstract: A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 26, 2023
    Assignee: TELEDYNE LECROY, INC.
    Inventors: Aaron Masters, Kevin Lemay, Chuck Tuffli
  • Patent number: 11822497
    Abstract: The disclosure provides a USB device, a USB cable, and a USB repeater. The USB cable or the USB device includes a USB connector and the USB repeater. The USB repeater may gain a signal of a differential pin pair of the USB connector. The USB repeater may monitor a signal of a configuration channel pin of the USB connector. The USB repeater selectively runs in one of a plurality of working modes corresponding to a plurality of protocols according to a monitoring result.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: November 21, 2023
    Assignee: GENESYS LOGIC, INC.
    Inventor: Ching-Hsiang Lin
  • Patent number: 11822494
    Abstract: A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: November 21, 2023
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Manfred Kunz, Markus Althoff, Xiongzhi Ning
  • Patent number: 11809353
    Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 7, 2023
    Assignee: INTEL CORPORATION
    Inventors: Kevan A. Lillie, Shlomi Lalush, Yaakov Dalsace, Adee Ofir Ran, Assaf Benhamou, David Golodni, Itay Tamir, Amir Laufer
  • Patent number: 11804679
    Abstract: An energy module is disclosed. The energy module includes a hand-switch circuit, a surgical instrument interface coupled to the hand-switch circuit, and a control circuit coupled to the surgical instrument interface and the hand-switch circuit. The control circuit is configured to control the hand-switch circuit to communicate with a surgical instrument coupled to the hand-switch circuit using a plurality of communication protocols over a single wire. The control circuit is configured to control the hand-switch circuit to supply power to the instrument over the single wire.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 31, 2023
    Assignee: Cilag GmbH International
    Inventors: Joshua Henderson, Joshua P. Morgan, Andrew W. Carroll, Jeffrey L. Aldridge, Eitan T. Wiener, James M. Vachon
  • Patent number: 11797464
    Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh M. Sankaran
  • Patent number: 11782865
    Abstract: An integrated circuit can be used to regulate data flow in a computing system. The integrated circuit can receive input data via a first interface associated with a first type of bus protocol and provide output data via a second interface associated with a second type of bus protocol. Size of the input data and the output data may vary based on the corresponding protocols. The integrated circuit can receive, via the first interface, an input data size for a write transaction to store the input data in a data storage unit. The integrated circuit can also receive a requested data size, via the second interface, to provide the output data for a read transaction. The integrated circuit can also generate an actual size of the output data based on the requested data size, the input data size, and size of the stored input data.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 10, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Gal Kochavi, Benny Pollak
  • Patent number: 11775468
    Abstract: A method for transmitting data between a peripheral device and a data acquisition unit, the data acquisition unit having a configurable communication interface via which the data are transmitted according to one of a number of defined communication protocols, includes: carrying out a communication protocol analysis by the peripheral device upon connection to a power supply; and carrying out an adaptation of the configurable communication interface of the peripheral device after detection of a communication protocol, providing a detected communication protocol, used by the data acquisition unit in order to carry out data exchange according to the detected communication protocol.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: October 3, 2023
    Assignee: PHOENIX CONTACT GMBH & CO. KG
    Inventor: Klaus Wessling
  • Patent number: 11768787
    Abstract: This application relates to methods and apparatus for transfer of data between a host device (400) and a peripheral device (300) via a USB Type-C connector (100; 304) of the host device. A data controller is described that has a path controller (309, 310; 706) for establishing signal paths between circuitry of the host device and contacts (101) of said USB Type-C connector. The path controller is operable in at least first and second modes. In the first mode the path controller establishes separate signal paths to each of at least first, second, third and fourth contacts (A6, A7, B6, B7) of the USB Type-C connector and a plurality of the established signal paths are for transfer of analogue audio data. In the second mode the path controller establishes a pair of signal paths to only a subset of said first to fourth contacts to provide a differential digital data path.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 26, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Robert David Rand, Graeme Gordon Mackay, Andrew James Howlett
  • Patent number: 11757763
    Abstract: A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 12, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Igor Gorodetsky, Hess M. Hodge, Timothy J. Johnson
  • Patent number: 11755520
    Abstract: An information handling system may include a host system including a first root complex, a management controller including a second root complex, a network interface controller, and at least one switching circuit. The information handling system may be configured to, in response to the host system being powered on: couple the network interface controller to the management controller via the first root complex; and wherein the information handling system is further configured to, in response to the host system being powered off: activate the at least one switching circuit to couple the network interface controller to the management controller via the second root complex.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: September 12, 2023
    Assignee: Dell Products L.P.
    Inventors: Zheng Zhang, Mahmoud B. Ahmadian
  • Patent number: 11748292
    Abstract: Various embodiments disclosed herein provides method and system for low latency FPGA based system for inference such as recommendation models. Conventional models for inference have high latency and low throughput in decision making models/processes. The disclosed method and system exploits parallelism in processing of XGB models and hence enables minimum possible latency and maximum possible throughput. Additionally, the disclosed system uses a trained model that is (re)trained using only those features which the model had used during training, remaining features are discarded during retraining of the model. The use of such selected set of features thus leads to reduction in the size of digital circuit significantly for the hardware implementation, thereby greatly enhancing the system performance.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: September 5, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Piyush Manavar, Manoj Nambiar
  • Patent number: 11741039
    Abstract: A PCIe device and a method of operating the same are provided. The PCIe device may include a throughput calculator configured to calculate a throughput of each of a plurality of functions, a throughput analysis information generator configured to generate throughput analysis information indicating a result of a comparison between a throughput limit and the calculated throughput, a delay time information generator configured to generate a delay time for delaying a command fetch operation for each function based on the throughput analysis information, a command lookup table storage configured to store command-related information and a delay time of a function corresponding to a target command, the command-related information including information related to the target command to be fetched from a host, and a command fetcher configured to fetch the target command based on the command-related information and the delay time of the corresponding function.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 29, 2023
    Assignee: SK hynix Inc.
    Inventor: Yong Tae Jeon
  • Patent number: 11734210
    Abstract: A computer booting apparatus includes a computer processor, a computer memory coupled to the computer processor, and a communication port coupled to the computer processor. The computer processor is configurable for operation in a host mode and a device mode. The host mode connects to an external computer processor and an external computer memory via the communication port, checks for a new image file or a revised image file stored in the external computer processor or the external computer memory, and loads the new image file or the revised image file into the computer memory. The device mode boots a device via the communication port using the new image file or the revised image file.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 22, 2023
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Gustavo Labbate Godoy, Carlos Eduardo Dias Duarte, Denis Leite Gomes
  • Patent number: 11726940
    Abstract: A system for communicating with removable components may include an electronic controller and a removable component having an identifier and configured to communicate with the electronic controller. The removable component may be configured to transmit the identifier to the electronic controller via a first communication channel. The electronic controller may be configured to transmit a confirmation to the removable component after receipt of the identifier. The removable component may be configured to transmit information to the electronic controller via at least one of the first communication channel and/or a second communication channel, after receipt of the confirmation.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: August 15, 2023
    Assignee: Lear Corporation
    Inventors: Raúl Ricart, Antoni Ferré Fàbregas, Jeffrey A. Jones