Patents Examined by Kim T. Huynh
  • Patent number: 11372790
    Abstract: A data processing system is implemented with a backup PCI Express system, which is able to take over as the primary PCI Express system for ensuring that an endpoint device continues to function in a desired manner when a root complex in the primary PCI Express system is no longer functioning correctly or is deactivated for maintenance. The endpoint device is coupled to the primary root complex and a backup root complex through a multiplexer. When a failure or shutdown of the primary root complex is detected, the multiplexer is signaled to switch the communication of data from occurring between the primary root complex and the endpoint device to then occur between the backup root complex and the endpoint device. A PCI Express Link may be utilized to communicate such a failure or shutdown and/or to transfer information from the primary PCI Express system to the backup PCI Express system when the switch occurs.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 28, 2022
    Assignee: NXP USA, INC.
    Inventors: Michael Johnston, Dinghui R. Nie, Joseph S. Rebello
  • Patent number: 11321263
    Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Gregory K. Chen
  • Patent number: 11294846
    Abstract: In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Kenneth P. Foust
  • Patent number: 11288227
    Abstract: A DRP determining method is provided. The method includes the following steps. Firstly, a first DRP electronic device and a second DRP electronic device are connected by a USB Type-C line. Then, the first DRP electronic device is set to one of a host and a device. Then, the second DRP electronic device is set to one of the host and the device. When the connection between the first DRP electronic device and the second DRP electronic device is disconnected and then re-connected, at least one of the first DRP electronic device and the second DRP electronic device is set to the other one of the host and the device.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 29, 2022
    Assignee: Qisda Corporation
    Inventors: Kuan-Hung Chen, Min-Yi Hsieh
  • Patent number: 11275607
    Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 15, 2022
    Assignee: Arm Limited
    Inventors: Peter Richard Greenhalgh, Antony John Penton
  • Patent number: 11275704
    Abstract: A communication system comprising: a digital serial bus, and a master device and at least one slave device connected to the bus. The master and the slave(s) are adapted to communicate according to a predefined communication protocol. The master is adapted for transmitting a continuous bitstream in the form of a plurality of frames, such that each frame comprises one or more words. Each word has a constant time duration, with the first word of each frame being a unique word transmitted by the master for indicating the start of a frame. One or more bits each word is transmitted by the master as a dominant bit; a non-dominant bit, for allowing the at least one slave to overwrite. The at least one slave is adapted for overwriting in the continuous bitstream some non-dominant bits to transmit data in a quasi-synchronous manner.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 15, 2022
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Mathieu Poezart, Zsombor Lazar, Antonius Duisters
  • Patent number: 11269803
    Abstract: A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 8, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Le-Sheng Chou, Sz-Chin Shih, Shuen-Hung Wang
  • Patent number: 11237989
    Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element. The instructions may further configure the processor to classify the USB element as only a producer of power, evaluate whether an enumeration process is initiated within a timeout period, and if so, assign the USB element as a USB host.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 1, 2022
    Assignee: Microchip Technology Incorporated
    Inventors: Atish Ghosh, Mark Gordon, Ken Nagai, Larisa Troyegubova
  • Patent number: 11232060
    Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Kenneth P. Foust
  • Patent number: 11232053
    Abstract: A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 25, 2022
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Darren Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma
  • Patent number: 11232057
    Abstract: The present application is directed to a television device and a control method therefor. The television device comprises an SOC chip, a DFP interface thereof being connected to a switch module via a USB D+/D? differential pair, and the USB D+/D? differential pair between the DFP interface and the switch module being a first channel; a USB Type-C interface main control module provided with a UFP interface, the UFP interface being connected to the switch module via a USB D+/D? differential pair, and the USB D+/D? differential pair between the UFP interface and the switch module being a second channel; and a USB Type-C interface connected to the switch module via a USB D+/D? differential pair. The USB Type-C interface main control module is also connected to the switch module via a control signal line.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: January 25, 2022
    Assignee: Hisense Visual Technology Co., Ltd.
    Inventor: Xuebin Sun
  • Patent number: 11232059
    Abstract: In example implementations, an apparatus is provided. The apparatus includes a first interface, an upstream device detector, a second interface, and a processor. The first interface receives a multi-channel connection. The upstream device detector is to detect a connection to external graphical processor unit (eGPU) via the first interface. The second interface is to connect a peripheral device that transmit data over the multi-channel connection via the first interface through the eGPU and to a host computer. The processor disables a portion of the multi-channel connection on the first interface when the upstream device detector detects the connection to the eGPU.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: January 25, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Roger D. Benson, Ho-sup Chung
  • Patent number: 11232048
    Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 25, 2022
    Assignee: SILICON MOTION INC.
    Inventor: Chao-Kuei Hsieh
  • Patent number: 11221975
    Abstract: A storage control system receives an I/O request from a client for accessing storage resources that are logically divided into device groups, and determines a resource token request value associated with the I/O request and a target device group to which the I/O request is directed. The storage control system determines a number of allowed resource tokens to allocate to the client as a function of (i) the resource token request value, (ii) a sum total of resource tokens requested by other clients for accessing the target device group, and (iii) a total amount of resource tokens currently allocated to the target device group to which the I/O request is directed. The storage control system sends the determined number of allowed resource tokens to the client to thereby enable the client to limit a number of inflight I/O requests that the client issues to the storage control system.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 11, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Avi Puder, Itay Keller, Galina Tcharny, Dvir Koren, Jonathan Sahar, Benjamin Grimberg
  • Patent number: 11210258
    Abstract: An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 28, 2021
    Inventor: Christian Cicerone
  • Patent number: 11194741
    Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 7, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Cheng-Chih Wang, Chih-Ping Lu, Yung-Chi Lan, Chun-Chi Chen
  • Patent number: 11183991
    Abstract: Described herein are nodes, sub-systems and systems of nodes for use in a dynamic node based computer. In some embodiments, nodes include: one or more signal receivers for detecting or receiving one or more input signals from one or more signal sources, one or more signal transmitters for selectively connecting and transmitting signals to one or more other nodes; and a threshold device configured to control the selective operation of the signal transmitter based on a threshold derived from one or more characteristics of the input signals. More complex variations of the nodes include the addition of threshold manipulation devices, signal amplifiers or dampeners, control devices, or computational devices. Also described herein are machines or devices built from one or more such nodes.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: November 23, 2021
    Inventor: Parker Wilde Stroh
  • Patent number: 11176073
    Abstract: A data processing apparatus includes a power-source controller, a data processing device, a physical-layer section, a communication controller, and a state controller. The power-source controller controls a first power-source setting and a second power-source setting. The second power-source setting causes less electric power consumption than the first power-source setting. The communication controller performs the communication with the data processing device through a predetermined communication path and the physical-layer section under the first power-source setting. The communication controller stops the communication with the data processing device through the communication path and the physical-layer section under the second power-source setting. The state controller maintains the second communication state with respect to the data processing device side of the communication path while electric power supply to the physical-layer section is reduced under the second power-source setting.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 16, 2021
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Syuhei Mitani, Akira Nakayama
  • Patent number: 11176069
    Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Helena Deirdre O'Shea, Camille Chen, Vijay Kumar Ramamurthi, Alon Paycher, Matthias Sauer, Bernd W. Adler
  • Patent number: 11176071
    Abstract: A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 16, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: David G. Wright, Shopitham Ram