Abstract: A bus pipeline structure comprises: an n-channel multiplexer at a transmitting end works in an n times of clock domain of a transmitting chiplet; the n-channel multiplexer sends a data flow from the transmitting chiplet to an n-channel de-multiplexer at a receiving end, the n-channel de-multiplexer inputs the received data flow into a first register in an idle state among at least two registers at the receiving end, the first register outputs the received data flow to a receiving chiplet; after a receiving state machine at the receiving end determines that the n-channel de-multiplexer sends the received data flow to the first register, the receiving state machine at the receiving end sends a bus release flag to a transmitting state machine at the transmitting end, and the transmitting state machine receiving the bus release flag controls an n-channel multiplexer to transmit the data flow in a next clock cycle.

Abstract: A system can include a serial, full-duplex, synchronous peripheral communication interface composed of four communication lines that communicatively couple a host processor to an optical sensor, the four communication lines including: a clock (CLK) line; a chip select (CS) line; a host output (MOSI) line; and a sensor output (MISO) line, the MISO line operating according to the following conditions when the CS line is selected: provide a service register data indicating when one or more predetermined conditions have occurred prior to receiving any commands from the host processor; provide a state register data defining the one or more predetermined conditions that occurred; and in response to receiving a command from the host processor received after the service register data and state register data is provided, the command requesting input device operational data, provide the operational data to the host processor.

Abstract: A plurality of virtual processor threads are executed on the plurality of physical processor threads. In a data structure, information pertaining to a plurality of interrupt sources in the data processing system is maintained. The information includes a historical scope of transmission of interrupt commands for an interrupt source. Based on an interrupt request from an interrupt source, an interrupt master transmits a first interrupt bus command on an interconnect fabric of the data processing system to poll one or more interrupt snoopers regarding availability of one or more of the virtual processor threads to service an interrupt. The interrupt master updates the scope of transmission specified in the data structure based on a combined response to the first interrupt bus command. The interrupt master applies the scope of transmission specified in the data structure to a subsequent second interrupt bus command for the interrupt source.

Abstract: A network architecture including a streaming array that includes a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture including a network storage of the streaming array. The network architecture including a PCIe fabric of the streaming array configured to provide direct access to the network storage from a plurality of compute nodes of the streaming array. The PCIe fabric including one or more array-level PCIe switches, wherein each array-level PCIe switch is communicatively coupled to corresponding compute nodes of corresponding compute sleds and communicatively coupled to the network storage. The network storage is shared by the plurality of compute nodes of the streaming array.

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: Provided are an apparatus and a method for controlling an interrupt rate for a processor based on processor utilization. Accordingly, it is possible to improve an I/O response latency and improve energy efficiency.

Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.

Abstract: A production line test method, system and device for a PCIE Switch product, and a medium. The method comprises: connecting to ports of a target PCIT Switch product using cables according to a preset rule, and controlling a target configuration file to run using a target controller such that the target PCIE Switch product enters a test state, wherein the target configuration file is a file pre-stored in the target PCIE Switch product, and the target controller is a controller pre-connected to the target PCIE Switch product; reading the current running information of the target PCIE Switch product and determining whether the current running information satisfies a preset condition; and if yes, determining that a production line of the target PCIE Switch product is normal. Hence, the method can greatly improve the test efficiency of a production line of a target PCIE Switch product.

Abstract: Methods and apparatus for efficient scaling of fabric architectures such as those based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters. In one aspect, methods and apparatus for using Non-Transparent Bridge (NTB) technology to export Message Signaled Interrupts (MSIs) to external hosts are described. In a further aspect, an IO Virtual Address (IOVA) space is created is used as a method of sharing an address space between hosts, including across the foregoing NTB(s). Additionally, a Fabric Manager (FM) entity is disclosed and utilized for programming e.g., PCIe switch hardware to effect a desired host/fabric configuration.

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

Abstract: A storage controller includes a processing device to send a Non-Volatile Memory Express over Fibre Channel (NVMe/FC) command to a submission queue without routing the NVMe/FC command through a kernel space, the submission queue being reserved for direct access by an initiator device to a user space of the storage controller.

Abstract: One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

Abstract: A slave device coupled to a master device via a bus and including a serial interface, a code generator circuit, and a control circuit is provided. The serial interface is configured to be coupled to the bus. The code generator circuit is configured to generate a unique code. The control circuit is coupled between the serial interface and the code generator circuit. In a set mode, the control circuit triggers the code generator circuit to generate the unique code. In an operation mode, the control circuit determines whether to perform commands provided by the master device according to the unique code.

Abstract: A tracking method, an apparatus, a device, and a machine-readable medium are provided. The method specifically includes: writing a tracking result of an activity of an operating system and/or a running activity of a program into a buffer when an interrupt is disabled; and reading and sending the tracking result from the buffer when the interrupt is enabled. The embodiments of the present disclosure can effectively shorten the maximum time during which interrupts are disabled for an operating system, and thereby can effectively improve the performance of the operating system and/or a program.

Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.

Abstract: Technologies for compressing communications for accelerator devices are disclosed. An accelerator device may include a communication abstraction logic units to manage communication with one or more remote accelerator devices. The communication abstraction logic unit may receive communication to and from a kernel on the accelerator device. The communication abstraction logic unit may compress and decompress the communication without instruction from the corresponding kernel. The communication abstraction logic unit may choose when and how to compress communications based on telemetry of the accelerator device and the remote accelerator device.

Abstract: This wireless communication device includes: a wireless communication unit of which operation is allowed to be activated and stopped; a determination unit configured to determine whether or not a measurement result by a sensor satisfies a predetermined condition; and a controller configured to perform control of, when the determination unit has determined that the predetermined condition has been satisfied, activating the wireless communication unit of which operation has been stopped, and causing the wireless communication unit to transmit the measurement result or a determination result by the determination unit.

Abstract: System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

Abstract: A device for controlling a transfer of information from a plurality of electronic components through a communication bus to a host device, comprising a chain of processing blocks connected to the electronic components, each of the processing blocks associated with one, or a set, of the electronic components, which processing blocks are arranged such that during the transfer of information an authorization signal propagates through the chain of processing blocks and, when the authorization signal encounters a processing block associated with one of the electronic components or one of the sets of electronic components which contains an information value to be transferred, effecting the transfer of the information value through the communication bus to the host device. The processing blocks are arranged to coordinate their processing in accordance with a clock signal generated independent of a propagation status of the authorization signal within the chain of processing blocks.

Abstract: Aspects are directed to systems in which control node communicates through a peripheral-side wired communications bus for data communications with other bus-coupled nodes. The control node acts as a master with a main-circuit domain during an initialization mode and when the main-circuit domain is deactivated, and acts as a slave, after completion of the initialization mode and when the main-circuit domain is not deactivated. An isolation circuit is used to isolate the main-circuit domain from the control node and, while the main-circuit domain is deactivated, to facilitate communications over the peripheral-side wired communications bus between the control node and another node connected to the peripheral-side wired communications bus.