Abstract: A pointer representation includes a permission field to define capabilities of the system in processing the data to which an address in the pointer of representation points. Bounds of the memory segment to which the capabilities apply are defined by a block field, which defines a block size, and a length field, which defines a number of blocks of that size within the segment of memory. To permit computation of the full range of addresses to which the capability applies, a finger field is included to denote the block of the segment of memory to which the address points. An increment-only bit may cause the system to preclude any negative offsets from the address in the pointer representation. Subsegments within a segment may be further defined by additional block, length and finger fields.

Abstract: Various methods and systems for implementing a sectored least recently used (LRU) cache replacement algorithm are disclosed. Each set in an N-way set-associative cache is partitioned into several sectors that each include two or more of the N ways. Usage status indicators such as pointers show the relative usage status of the sectors in an associated set. For example, an LRU pointer may point to the LRU sector, an MRU pointer may point to the MRU sector, and so on. When a replacement is performed, a way within the LRU sector identified by the LRU pointer is filled.

Abstract: Memory pool management may be provided by allocating storage blocks and handles in different parts of a larger memory pool. Two variable size sub-pools may be provided within the memory pool: a storage block sub-pool and a handle sub-pool. Each sub-pool has a variable size and may be allowed to grow until their combined size reaches the size of the memory pool. Both sub-pools may be allowed to grow into the same unused memory space. When a memory request is received from a program, the storage block sub-pool and handle sub-pool may be enlarged to accommodate the request. A storage block and a handle may be allocated to the program from the storage block and handle sub-pools, respectively.

Abstract: A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register.

Abstract: A specific-accessible service and a commonly accessible service can co-exist while ensuring the security thereof. It is assumed that a common area of a company A's issued IC card has registered therein an electronic value (corresponding to 1000 yen and a specific area thereof has registered therein a specific-accessible service point of 50 (corresponding to 50 yen). With respect to the commonly accessible electronic value and specific-accessible service point that are registered in the enterprise A's issued IC card, addition and subtraction can both be executed using a specific key A registered in the company A's terminal apparatus. However, in each of the respective cooperating companies' terminal apparatus, with respect to the commonly accessible electronic value, only subtraction processing is possible using a common key registered therein.

Abstract: A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Abstract: In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions, a burst controller for executing the burst instructions, a burst instructions element for providing burst instructions in a sequence for execution by the burst controller, and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute. Burst instructions are provided by the first processor to the burst instructions element and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the data buffer in accordance with burst instructions executed by the burst controller.

Abstract: A DRAM includes a set of secondary sense amplifiers as well as primary sense amplifiers coupled to respective digit lines of a DRAM array. The secondary sense amplifiers are coupled to the digit lines of an array through isolation transistors so that the secondary sense amplifier can be selectively isolated from the digit lines of an array. The DRAM also includes a refresh controller that periodically refreshes the DRAM on a row-by-row basis, and a command decoder that causes the refresh to be aborted in the even a read or a write command is received by the DRAM during a refresh. The refresh is aborted by saving the data stored in the row being refreshed in the secondary sense amplifiers and then isolating the sense amplifiers from the array. The memory access is then implemented in a normal manner. Since the DRAM can be accessed without waiting for the completion of a refresh in progress, the DRAM can be used as a cache memory in a computer system.

Abstract: A coupling circuit for coupling a data signal from a first clock domain defined by a first clock signal to a second clock domain defined by a second clock signal. A phase comparator determines whether the first clock signal leads the second clock signal. If so, the data signal is clocked from the first clock domain at a time after a start signal that is later than if the clock signal does not lead the second clock signal. Alternatively, if the first clock signal leads the second clock signal, the data signal may be clocked to the second clock domain at a time after a start signal that is earlier than if the clock signal does not lead the second clock signal.

Abstract: The present invention is directed to a disk drive which can assert control over the information content supplied in response to a read request from the host by performing a selective translation of addresses received from the host. The disk drive can include hardware, firmware, or a combination thereof, to unambiguously detect a command block to read a predetermined location on the drive. The drive, upon detecting occurrence of a predetermined address included in the command block, translates the address to initiate a read from an alternate, substitute location information stored at the substitute location is returned to the requesting host in satisfaction of the host's request. The information can be blocks of data, such as audio/video data, or can be executable code including, but not limited to, code used to boot a substitute operating system stored at a location known only to the drive.

Abstract: A data processing network, server device, and method in which an application program memory usage parameter is monitored where the parameter is indicative of the server device's performance and loading. If the memory usage parameter exceeds a specified criteria, the amount of the system memory available to the application program is reduced and a physical section of memory is deactivated to save power. The parameter may represent the server application's file cache hit rate and reducing the amount of memory available to the application program may include reducing the file cache size. Reducing the file cache size may include invalidating file cache data based upon a purge criteria that indicates when the data was most recently accessed. If the memory usage parameter falls below the specified criteria, additional system memory made be activated and made available to the application program to maintain performance at a desired level.

Abstract: The present method for predictive caching operation determines a time-based pattern of a high-access period for a web page, and pre-fetches the web page into a cache before the high access period begins. A table is generated where the table comprises a URL, a time of last access and a time stamp of the pre-fetched web page. When a request for a web page is made, the requested web page's URL and time stamp are checked with the URL and time stamp listed in the table to determine whether any modification has been made. The web page which has been modified is downloaded into the cache.

Abstract: Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy.

Abstract: The present invention relates to a system and a method of memory management of data consistency relating to a main memory (4) accessible by at least two processors (1, 2), as well as an associated multiprocessor network. The management system comprises an assembly for management of shared access of the processors to a common area (9) of the main memory, referred to as the exchanges area, at least one copy module (12, 13) intended for performing a data copy between at least one first processor comprising at least one cache memory and the exchanges area and at least one transfer module (12, 13) intended for performing a transfer of data between the exchanges area and at least one second processor. Triggering means controlled by the second processors trigger the copy modules and transfer modules when the first processors submit requests involving transfers of data between the first and second processors.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A system and method for indexing and retrieving objects stored in a cache on a persistent medium (e.g., a disk) introduces the concepts of probable hits and asynchronous retrieval of cached objects during a search. Each index entry is a “bucket” for holding corresponding cached objects whose keys are convertible by means of a lossy compression mechanism to an identification (“ID”) of the index entry. When a request for a data object is received, the cached objects in the bucket of the index entry corresponding to the requested object key are checked to see if any of them is the requested object. For a cached object likely to be the requested object, an asynchronous retrieval operation is performed to retrieve that cached object from the persistent medium, and its key is compared with the requested object key. To further reduce the memory space required for implementing the index, a lightweight synchronization scheme is used instead of conventional semaphore objects.

Abstract: Systems and methods are disclosed in which a computer system having main memory and persistent memory is caused to perform a method for caching related objects. The computer system receives a plurality of objects from an origin server and computes a hash value based on source information about an object. Then the computer system stores the object based on the hash value with other related objects. Additionally, a computer system consistent with the present invention may retrieve related objects from the cache by performing a batch read of related objects.

Abstract: Efficient memory operation is provided by maintaining alignment with cache line boundaries in response to a read command. A prefetching scheme is used to limit the amount of operations needed to respond to a read command. In addition, the prefetch amount is initially adjusted where the starting address of the read request falls in between cache line boundaries. The adjusted read amount is determined based on the misaligned portion from the starting address of the read request to the nearest cache line boundary outside of the requested data block, such that the adjusted read amount ends on a cache line boundary. Subsequent read requests to the same data block will thereby begin at the last cache line boundary and end upon a subsequent cache line boundary by providing the pre-configured prefetch data amount corresponding to the requesting master device.

Abstract: A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a security circuit for controlling a security function which activates or deactivates at least a part of the memory space according to whether, in the case where an address input to the security-circuit matches at least one key-address included in the security circuit, data stored in the address in the memory space is manipulated under a condition equal to a predetermined condition or under a condition not equal to the predetermined condition.

Abstract: Provided is a method, system, and program for superimposing a data record in a first data format onto a storage space in a second data format. A plurality of control blocks are built in memory indicating operations to perform to transfer components of the data record in the first data format to locations in memory in the second data format. A data transfer device is signaled to access the control blocks built in the memory. The data transfer device accesses the control blocks in the memory and then transfers components of the data record in the first data format to the memory to be stored in the second data format according to the operations indicated in the control blocks.