Abstract: A memory system and a set of user-level instructions that are callable from user-level code for converting virtual addresses to physical addresses and conveying the physical addresses to peripheral devices without requiring a system call. The system uses a translation look-aside buffer (TLB) implemented in a microprocessor. The contents of the TLB can be updated while processes are executing, allowing for virtual/physical addresses to be constantly updated and loaded into the buffer without requiring that the buffer be too large. Pages in use per transaction or user-level job are “pinned down” and pinned page counts per transaction or user-level job, as well as overall counts are maintained.

Abstract: A method for improving performance of a multiprocessor data processing system having processor groups with shared caches. When a processor within a processor group that shares a cache snoops a modification to a shared cache line in a cache of another processor that is not within the processor group, the coherency state of the shared cache line within the first cache is set to a first coherency state that indicates that the cache line has been modified by a processor not within the processor group and that the cache line has not yet been updated within the group's cache. When a request for the cache line is later issued by a processor, the request is issued to the system bus or interconnect. If a received response to the request indicates that the processor should utilize super-coherent data, the coherency state of the cache line is set to a processor-specific super coherency state.

Abstract: The present invention provides a mechanism whereby caching operations, such as prefetch and copyback operations, can be initiated by an external direct memory access (DMA) controller. This allows the DMA controller to govern the inclusion as well as exclusion of data from a processor cache in such as way as to avoid unnecessary cache faults, and to thereby improve system performance. Thus, the present invention effectively provides a synchronization mechanism between an external DMA controller and a processor cache.

Abstract: A write cache that reduces the number of memory accesses required to write data to main memory. When a memory write request is executed, the request not only updates the relevant location in cache memory, but the request is also directed to updating the corresponding location in main memory. A separate write cache is dedicated to temporarily holding multiple write requests so that they can be organized for more efficient transmission to memory in burst transfers. In one embodiment, all writes within a predefined range of addresses can be written to memory as a group. In another embodiment, entries are held in the write cache until a minimum number of entries are available for writing to memory, and a least-recently-used mechanism can be used to decide which entries to transmit first. In yet another embodiment, partial writes are merged into a single cache line, to be written to memory in a single burst transmission.

Abstract: A system and method for managing a cache space employs a space allocation and recycling scheme that has very low complexity for each data caching transaction regardless of the size of the data set, is virtually fragmentation free, and does not depend on garbage collection. The cache space is treated as a linear space with its two ends connected in the manner of a cyclic queue. The reclaiming and allocation of cache space for writing new objects proceeds as an “allocation wave” that sweeps in a pre-selected direction over the “circular” cache space. As the allocation wave moves along the circular space, the space used by existing objects are reclaimed for writing new objects except for those existing objects that for some reason are not to be written over. Those existing objects to be passed over by the allocation wave are viewed as “interruptions” to the generally first-in-first-out (FIFO) allocation scheme for writing new objects into the circular cache space.

Abstract: The invention includes a disk drive that includes a controller that is connected to a physical media. The controller includes a processor that is connected a controller memory. The disk drive is responsive to communication from a host computer. The controller memory includes a set of computer program instructions and data to write data to the disk drive memory as a linear sequence of data bytes in response to a write data command from the computer. In yet other embodiments, the invention uses hardware data compression to compress data before it is written to a disk drive, and to decompress data before compressed data is returned to a computer.

Abstract: A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In the coherent mode, the memory controller ensures that the data stored in system memory is accurately and precisely mirrored in all subservient copies of that data as might typically be stored in agent cache memories. Using, for example, a MESI type protocol, the memory controller limits access to memory so that only an “owner” or a particular portion or line of memory has write access and that, during the extension of these write privileges, no other agent has a valid copy of the data subject to being updated. Thus, the memory controller implements a first set of rule in the coherent mode of operation to insure that all copies of data stored by the agents are coherent with data stored in the memory.

Abstract: A method of and system for concurrently processing multiple memory requests. The first and second memory requests contain a linear address. A search for the cache entry in a cache block is issued in response to the linear address. After locating the cache entries associated with the memory requests, there is an update of the least recently used status for the cache entries with reference to the memory requests.

Abstract: A performance enhancing change-to-dirty operation (CTD) is disclosed wherein contention among several processors trying to gain ownership of a block of data is obviated by arranging the CTD to always succeed. A method and a system are disclosed where a processor in a multiprocessor system having a copy of data gains assured ownership of data that the processor may then write. The method provides for the possibilities of conditions that may exist and provides a scenario that the requesting processor may have to wait for the ownership. Conditions are handled where the memory is the “owner” of the data and where other processor are requesting ownership, and where copies of the data exist at other processors. The method provides for messages to other processor having copies of the data informing them that the data is now invalid.

Abstract: A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.

Abstract: Described are techniques for use in determining a dynamic mirror service policy (DMSP) for a plurality of mirror devices. The DMSP determines which of the plurality of mirror devices services I/O operations associated with a logical volume (LV), such as a read operation, at a particular point in time. The particular DMSP may subsequently be recalculated using device statistics from a different time interval. Part of determining a DMSP includes using device statistics to determine the activity level of each LV. The activity levels of multiple LVs may be combined to determine the activity level associated with a particular mirror device. A mirror device is selected if it has the minimum activity of all the plurality of mirror devices. Seek minimization processing is performed to minimize the distance between LVs stored on a single mirror device. Parameters used in connection with determining a DMSP may be stored in a configuration file and may be dynamically modified.

Abstract: An improved shadow directory technique allocates storage space for directories in pairs in a logical volume. One of the spaces in each pair is used for a directory for locating data in the logical volume. The other space is reserved for an updated copy (shadow) of the directory if the directory is ever to be changed or updated. After the shadow directory is stored, it becomes a new directory for locating the data in place of the previous directory. The storage space containing the previous directory is unused, but retained as allocated for the next shadow directory, if needed. Since directory storage spaces are not deallocated, the improved shadow directory technique enables a simplified sequential-allocation storage management in a primarily data-add environment.

Abstract: A method, system, and apparatus for managing data elements in a storage area is disclosed. A storage area, with a first and second end, is provided for storing data elements. The data elements are stored in a first stack, also having a first and second end. Space in the storage area for the first stack includes a first space proximate the first end of the first stack, and a second space proximate the second end of the first stack. The storing of one of the data elements in the first stack includes selecting between storing in the first space or the second space, responsive to the relative sizes of the two spaces. Data elements are also stored in the storage area in a second stack. Space available in the storage area for data elements of the second stack includes the above mentioned first and second spaces, that is, the space proximate the first end of the first stack, and the space proximate the second end of the first stack.

Abstract: A memory system comprises a memory array having a plurality of memory locations; a plurality of write ports for writing to the memory array; write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, the write protection circuitry providing one write enable signal for each write port, the write enable signals being applied to the memory array; and circuitry for controlling the timing of the application of the write enable signals to the memory array, the circuitry for controlling the timing being upstream of the write protection circuitry.

Abstract: An arbitration system having a common resource and a first arbitration logic. The first arbitration logic includes a plurality of logic sections. Each one of the logic sections is fed a corresponding one of a plurality of request signals for the common resource. The logic sections produce, in response to request signals, a corresponding one of a plurality of grant signals. Each one of such sections has: a corresponding one of a plurality of first data storage elements, each one of such storage elements storing a corresponding one of the grant signals in response to first clock pulses, such stored grant signals being provided at outputs of the storage elements. The arbitration system includes a plurality of transmission channels, each one having an input coupled to a corresponding one of the outputs of the plurality of first data storage elements. The plurality of transmission channels pass the grant signals stored in the first data storage elements to outputs of the transmission channels.

Abstract: A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

Abstract: A system and method for defining rewriteable data storage media defined by ECMA Standard ECMA-272 2nd edition (1999) for 120 mm DVD rewriteable disk (DVD-RAM) as a write once data storage media and for storing data thereon. The apparatus consists of a data storage device for reading and writing data on the media, the media, a media type indicator in the media, two write protect flags in the user data area of the media, and programming to examine the two write protect flags prior to a write, erase, or format operation. If both flags match and the media type indicator is write once, the drive is prevented from writing to the user data area if both flags are in the data written state. If both flags do not match after two re-reads, an error message is generated. If both flags are in the data unwritten state, data is written to the user data area and both flags are set to the data written state.

Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

Abstract: Memory management method in which lifetimes are assigned to messages which are to be written into a memory, and in which, in addition, when the memory is full and further messages arrive those stored messages whose period of activation has expired the longest are cleared.