Abstract: A file control device having physical storage devices and logical storage devices, which prevents competition for access to the physical storage device and avoids a decline in performance. When adding a new block to the cache memory or when ejecting a block from cache memory, a block with the lowest access frequency out of data retained in a physical storage device having the lowest access frequency is determined for ejection. The file control device concurrently monitors storage device priority information in addition to data priority information to control transfer of data between the storage device and the cache memory.

Abstract: There is provided a computer that can safely rewrite any one of the areas where a boot program is stored with fewer actions in the self-mode. A nonvolatile memory is divided into a plurality of areas, each of which is separately erasable and includes a user area and a boot area designation flag indicating whether the corresponding user area is specified as a boot area. An area designation flag specifies the user area containing a boot program among a plurality of user areas. A CPU sets the value of the area designation flag based on the values of a plurality of boot area designation flags. When a system is started, the user area including the program for starting the operation of the CPU is determined based on the value of the area designation flag.

Abstract: Computer systems and methods that provide for cacheable above one megabyte system management random access memory (SMRAM). The systems and methods comprise a central processing unit (CPU) having a processor and a system management interrupt (SMI) dispatcher, a cache coupled to the CPU, and a chipset memory controller that interfaces the CPU to a memory. The memory includes system memory and the system management random access memory. The systems and methods un-cache the SMRAM while operating outside of system management mode, transfer CPU operation to system management mode upon execution of a system management interrupt (SMI), and change cache settings to cache the extended memory and system management random access memory with write-through. The systems and methods then change cache settings to cache the extended memory with write-back and un-cache the SMRAM upon execution of an resume instruction.

Abstract: When a data read request is made at a long unit (two words) in a data processing system including a plurality of data processing unit, a control unit, a plurality (for example, two) of memory devices, data is simultaneously read from both memory devices. While certain data is supplied to the requesting data processing unit, other data is stored in a register. At the next timing, the other data is supplied to the data processing unit from the register. In storing, one word data is stored in a register. At the next timing, this word data and the following word data is stored in memory devices, respectively, at the same time. Pre-loading data and priority changing operations reduce the occurrence of access collision.

Abstract: This Rambus DRAM has a power save function which is not restricted in using time and has a short setting time, by forcibly compensating for a lost capacitor value in a memory cell to have a predetermined value, when a power save mode is changed to a normal mode.

Abstract: A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A system and method for providing transaction management for writing operations on a data storage space, such as a cache, persistently tracks a “transient zone” that covers an active area in which write operations are being performed. The data storage space may be a linear space in which the operations of reclaiming space for writing new objects proceed as a wave. The “head” of the transient zone is set to stay ahead of the front of the wave, while the “tail” of the transient zone is set to stay behind or up to the active block at the rear edge of the active area. As the wave of space reclaiming travels along the data storage space, the head of the transient zone is moved from time to time to maintain a lead. The tail of the transient zone is also moved from time to time as writing operations are completed.

Abstract: In a system and method for linking and unlinking code fragments stored in a code cache, a memory area is associated with a branch in a first code fragment that branches outside the cache. If the branch can be set to branch to a location in a second code fragment stored in the cache, branch reconstruction information is stored in the memory area associated with the branch, and the branch instruction is updated to branch to the location in the second code fragment, thereby linking the first code fragment to the second code fragment. If it is determined that the previously linked branch should be unlinked, the first and second code fragments at that branch are unlinked by reading the information stored in the associated memory area at the time of linking, and using that information to reset the branch to its state prior to the linking.

Abstract: A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

Abstract: A storage array is described which is specifically adapted to support a specific set of instruction modes of a processor. A first set of storage cells have a write input and a single read output. Second and third sets of storage cells each have a write input and only two read outputs. A fourth set of storage cells each have a write input and only three outputs. All the write inputs are addressable in common by a single write address and the read outputs are individually selectable responsive to a read pointer.

Abstract: A storage system includes a physical storage system in the form of a number of disk storage units and a controller unit that handles data transfers between the disk storage units and one or more host data processing systems. Data is stored in mirrored fashion so that multiple copies of the data are available for fault tolerance and enhanced performance. The controller unit implements a logical volume management system that includes a plurality of logical volumes, each of which map to corresponding areas of storage of the disk storage units, thereby parsing the available physical storage. Received I/O write and read requests are assigned to one or another of the logical volumes, and therethrough data is written to or read from the corresponding disk storage unit or units. Usage of the disk storage units is monitored by the controller, and if one or more are found to be over-utilized, the number of logical volumes is increased to more finely parse the physical storage.

Abstract: The present invention relates to a method for controlling the access, in a computer, of a memory having an erasure frequently limited by blocks. This memory contains utility memory blocks (NB0, NB1) which are available for a user's access by an address conversion occurring through a pointer panel (AZTO). An erasure utility category (LN0, LN1023) is maintained in the form of a table in association with each address pointer maintained in the form of a table in association with each address pointer (AP0 AP1023). This erasure utility category is increased every time a predetermined erasure-state criteria is reached. The other pointing positions of the erasure utility categories (LN0 LN1023) are further explored in the pointer panel (AZTO) until a lower erasure utility category is found. The corresponding address pointer (AP0 AP1023) is then permuted with the one located at the output with the one located at the output pointer position (AP1).

Abstract: An arbitration system having a common memory region. The region has a plurality of refreshable data storage elements. The system includes a plurality of memory region controllers each one being adapted to request access to the common memory region. Each one of the controllers has a memory refresh section for refreshing the data storage elements in the common memory. An arbitration unit is responsive to the requests from the plurality of memory region controllers, for granting access to the controllers in a sequence. The sequence comprises granting access to operative ones of the controllers sequentially with the refresh section of less than all of the access granted controllers being granted access to the common memory region during in the sequence.

Abstract: The present method for selective web caching comprises the steps of generating a table, the table comprising a URL, a time of last access and a time stamp of a web page, the table further comprising a URL, time of last access and time stamp of elements found on the web page; when a request for a web page is made, checking the requested web page's URL and time stamp and URL and time stamp of the requested web page's corresponding elements with the URL and time stamp listed in the table to determine whether any modification has been made; and selectively downloading in a cache only those elements which are deemed to have been modified.

Abstract: A cache controller expresses a status of a data block by one of six statuses obtained by newly adding Writable Modified to Invalid, Shared, Exclusive, Modified, and Shared Modified. In response to a fetching request from a self system CPU for a data block having the status of Invalid I, when the data block having the status of Modified M is obtained from a cache apparatus of another system, the cache controller changes the status of the obtained data block from Invalid to Writable Modified. The cache controller also switches the status of the data block on the obtaining destination side from Modified to Invalid. As a result, the making of a status change notification to the other system in response to a subsequent storing request from the self system CPU, is unnecessary.

Abstract: Block-level storage is managed in a computerized storage system by recording into a write-ahead log a description of block-level updates made to data in a volume in a main memory and in a storage device of the computerized storage system. The write-ahead logging enables directory updates for each block-level write request to be logged, so the write request can be allowed to complete independently of other write requests.

Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

Abstract: A microprocessor is configured to continue execution in a special Speculative Prefetching After Data Cache Miss (SPAM) mode after a data cache miss is encountered. The microprocessor includes additional registers and program counter, and optionally additional cache memory for use during the special SPAM mode. By continuing execution during the SPAM mode, multiple outstanding and overlapping cache fill requests may be issued, thus improving performance of the microprocessor.

Abstract: A hardware configuration and methodology for serializing or partially serializing WRITE requests directed to a unified data set are subsequently distributed to one or more remote arrays containing a corresponding mirror unified data set. For each unified data set, one of the local disk arrays over which the unified data set is distributed is selected as a supervisor disk array, and a unified sequence number component is included within that supervisor disk array. WRITE requests generated by a local array to mirror unified data set data to a mirror unified data set must be associated with a unified sequence number, and the WRITE requests are therefore serialized or partially serialized by the unified sequence number component. Additional direct communications links are provided between the local arrays over which a unified data set is distributed both to facilitate WRITE-request serialization and to provide a redundant communications paths for added reliability.