Abstract: A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: A method for forming a via in a sapphire substrate with a laser machining system that includes an ultrafast pulsed laser source. The sapphire substrate is provided. Pulses of laser light are substantially focused to a beam spot on the first surface of the sapphire substrate such that each focused pulse of laser light ablates a volume of the sapphire substrate having a depth less than the substrate thickness. The beam spot of the focused laser light pulses is scanned over a via portion of the first surface of the sapphire substrate. The sapphire substrate is moved in a direction substantially normal to the first surface to control the volume of the sapphire substrate ablated by each pulse of laser light to be substantially constant. The pulsing and scanning steps are repeated until the via is formed extending from the first surface to the second surface of the sapphire substrate.

Abstract: In a plasma processing method, a correlation between substrate type data and optical data is obtained by using a multivariate analysis; substrate type data is obtained from optical data based on the correlation when initiating a plasma processing; and a substrate type is determined by using the obtained substrate type data. Further, a setting data set corresponding to the determined substrate type is selected from setting data sets, each for detecting a plasma processing end point of the plasma processing, each of the setting data sets being stored in advance in a data storage unit; an end point of the plasma processing is detected based on the selected setting data set; and the plasma processing is terminated at the detected end point.

Abstract: A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

Abstract: A method and apparatus for removing volatile residues from a substrate are provided. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a load lock chamber and at least one processing chamber coupled to a transfer chamber, treating a substrate in the processing chamber with a chemistry comprising halogen, and removing volatile residues from the treated substrate in the load lock chamber.

Abstract: An electronic substrate manufacturing method includes: forming a wiring pattern on a substrate; providing a mask with an opening for the substrate on which the wiring pattern has been formed; performing a specified treatment in a part area of the wiring pattern through the opening of the mask. The opening has a size based on an accuracy of an alignment between the substrate and the mask.

Abstract: A method for etching a dielectric layer over a substrate and disposed below a mask is provided. The substrate is placed in a plasma processing chamber. An etchant gas comprising O2 and a sulfur component gas comprising at least one of H2S and a compound containing at least one carbon sulfur bond is provided into the plasma chamber. A plasma is formed from the etchant gas. Features are etched into the etch layer through the photoresist mask with the plasma from the etchant gas.

Abstract: The manufacturing method of the present invention provides a silicon wafer, both sides of the wafer having a highly accurate flatness and small surface roughness, which is a single surface mirror-polished wafer with the front and rear surfaces of the wafer identifiable by visual observation, and excellent in flatness when held by a stepper chuck and the like. The manufacturing method of the present invention includes an etching process, a lapping process, and a double surface polishing process to simultaneously polish the front and rear surfaces of a wafer after the etching process. The polishing removal depth (A) of the wafer front surface is 5 to 10 ?m in the double surface simultaneous polishing process, and the polishing removal depth (B) in the rear surface is 2 to 6 ?m, and a difference between the polishing removal depth A and the polishing removal depth B is 3 to 4 ?m.

Abstract: In an apparatus and method of vapor etching, a sample (S) to be etched is located in a main chamber (107) from which the atmosphere inside is evacuated. Etching gas is input into the main chamber (107) for a first period of time. Thereafter, the etching gas is evacuated from the main chamber (107) and cooling/purging gas is input into the main chamber for a second interval of time. Thereafter, the cooling/purging gas is evacuated from the main chamber (107). Desirably, the steps of inputting the etching gas into the main chamber (107) for the first period of time, evacuating the etching gas from the main chamber, inputting the cooling/purging gas into the main chamber (107) for the second period of time, and evacuating the cooling/purging gas from the main chamber are repeated until samples have been etched to a desired extent.

Abstract: A method of processing a substrate that enables the amount removed of an insulating film to be controlled precisely, without damaging an electronic device. An insulating film on a substrate of a solid-state imaging device is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

Abstract: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.

Abstract: A method for etching doughnut-type glass substrates, which comprises laminating a plurality of doughnut-type glass substrates each having a circular hole at its center so that the circular holes form a cylindrical hole, and applying an etching treatment to inner peripheral edge surfaces of the plurality of the laminated doughnut-type glass substrates all at once by means of an etching liquid or an etching gas, wherein the etching liquid or the etching gas is supplied from one end of the cylindrical hole, made to flow in the cylindrical hole, and discharged from the other end of the cylindrical hole so that it is not in contact with exposed main surfaces of the doughnut-type glass substrates at both ends of the laminate consisting of the doughnut-type glass substrates.

Abstract: An alkali etching liquid for a silicon wafer that includes an aqueous solution of potassium hydroxide, and from 0.1 g/L to 0.5 g/L of diethylene triamine pentaacetic acid. Furthermore, the Fe concentration of the aqueous solution of potassium hydroxide is no more than 50 ppb. An etching method that including a step of etching a silicon wafer with a resistivity of no more than 1?·cm using the etching liquid.

Abstract: Rapid thermal processing apparatus methods are disclosed. In a disclosed apparatus, rapid thermal processing is carried out when the residual oxygen detected by a residual oxygen detector does not exceed a predetermined tolerance level. Accordingly, it is possible to prevent the contact resistance of the wafers from increasing due to the presence of excessive oxygen.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing the remaining hard mask pattern to expose an upper portion of the plug and have the upper portion protrude above the insulation layer, and forming a metal line over the protruding plug and around the upper portion of the plug.

Abstract: A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures.

Abstract: A method of manufacturing a semiconductor device. In this method, a concave portion is formed in one surface in the thickness direction of a primary base plate comprising a semiconductor substrate with a relatively large thickness dimension. Then, through-holes are formed by a reactive-ion etching process using as a mask an opening formed in an oxide film provided on the other surface in the thickness direction of the primary base plate. The opening has a narrow width in a region corresponding to the concave portion and a wide width in the remaining region. Thus, respective times necessary for the wide-width through-hole to penetrate through the primary base plate and necessary for the narrow-width through-hole to reach a bottom surface of the concave portion can be approximately equalized to complete the common etching process of the wide-width through-hole and the narrow-width through-hole approximately simultaneously.

Abstract: A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings.

Abstract: It is an object to provide a high-precision method for forming deep holes of elliptic pattern, which can improve hole directionality on the short diameter side, the hole directionality being possibly deteriorated as a result of excessive polymer deposition in the initial etching stage. The insulating film dry etching method is for treating a work on which a mask of elliptic pattern is formed with a fluorocarbon gas, wherein the etching process is divided into a first and second steps after the etching is started, the first step operating to deposit a polymer at a rate set lower than that in the second step, and controlling step time in accordance with ellipticity (long diameter/short diameter ratio) of the elliptic pattern.