Abstract: A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the device. In one embodiment, a heightened positive voltage and heightened negative voltage is applied to the semiconductor device while plasma etching is occurring to thereby induce charge to be removed from the semiconductor device.

Abstract: A method of manufacturing a semiconductor device, including the steps of forming one or more insulation films over a substrate, said one or more insulation films including an insulation film at a top thereof, coating the insulation film with a substrate processing agent, providing resist onto the insulation film coated with the substrate processing agent, lithographically forming a pattern of the resist, and dry-etching the insulation film by using the resist as a mask, wherein the substrate processing agent contains at least a solvent and an acid generating agent.

Abstract: The invention provides a chemical-mechanical polishing composition comprising a cationic abrasive, a cationic polymer, a carboxylic acid, and water. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition. The polishing composition exhibits selectivity for removal of silicon nitride over removal of silicon oxide.

Abstract: A method is provided for oxide removal from a substrate. The method includes providing the substrate in a process chamber where the substrate has an oxide layer formed thereon, and performing a sequential oxide removal process. The sequential oxide removal process includes exposing the substrate at a first substrate temperature to a flow of a first etching gas containing F2 to partially remove the oxide layer from the substrate, raising the temperature of the substrate from the first substrate temperature to a second substrate temperature, and exposing the substrate at the second temperature to a flow of a second etching gas containing H2 to further remove the oxide layer from the substrate. In one embodiment, a film may be formed on the substrate following the sequential oxide removal process.

Abstract: The present invention provides an aqueous composition useful for polishing copper interconnects on a semiconductor wafer comprising by weight percent up to 25 oxidizer, 0.05 to 1 inhibitor for a nonferrous metal, 0.01 to 5 complexing agent for the nonferrous metal, 0.01 to 5 modified cellulose, and balance water, wherein the composition is free of polyacrylic acid, the amount of modified cellulose providing a copper removal function and a wafer clear of copper.

Abstract: An integrated electronic circuit includes a cavity buried in a substrate. A surface of the substrate has a depression aligned above the buried cavity. The depression is filled with a material selected so that reflection of a lithography radiation on the substrate surface is attenuated. A resist layer is deposited on the circuit and then exposed to the radiation so that those resist portions which are located above the depression and those located away from the depression receive amounts of radiation that are below and above, respectively, the development threshold of the resist. An etching mask is therefore obtained on the circuit, which is aligned with respect to the cavity and its associated surface depression.

Abstract: A method for fabricating a semiconductor device includes forming a copper film above a surface of a substrate, forming on a polishing pad a material which contains copper, wherein said copper does not derive from said copper film, and after having formed the copper-containing material on said polishing pad, polishing said copper film by use of said polishing pad.

Abstract: Method for patterning a photoresist film in lithographic process including the steps of: coating the photoresist film on a substrate provided with an under layer; exposing the substrate; firstly developing the photoresist film; exposing a whole surface of the substrate; and secondly developing the photoresist film. The present method has effects on improving an accuracy of formation of pattern and preventing from scum, photoresist residues, and so on, with relatively low cost and short process time.

Abstract: In a vacuum processing chamber, an etching is performed on an object to be processed having at least a mask layer formed in a predetermined pattern and a Ti layer, as a layer to be etched, formed under the mask layer. During the etching, a first plasma processing is carried out to etch the Ti layer by using a plasma of an etching gas containing a fluorine compound at an inner pressure of the chamber of 4 Pa or less. Subsequently, a second plasma processing for dry cleaning is performed by using a plasma of a cleaning gas after the first plasma processing is completed. At this time, a deposit containing a Ti compound produced during the plasma processing is removed.

Abstract: An insulation film on a substrate is subjected to a plasma treatment using a gas containing at least either of a CH-based gas and a CO-based gas, whereby variations in the dielectric constant of the insulation film and adsorption of water onto the insulation film can be suppressed.

Abstract: The invention relates to a method for monitoring a manufacturing process, which by using a linear combination of measured variables with judiciously chosen weighting, produces a suitable (optimal) signal for determining each parameter. The extraction of the parameters from the measured variables is thus greatly simplified and in many cases becomes actually possible for the first time. According to the invention, large amounts of data may now be prepared, such that the crucial information (parameters) can be obtained from the data, almost in real time, or in real time.

Abstract: A chemical mechanical polishing composition contains 1) water, 2) optionally an abrasive material, 3) an oxidizer, preferably a per-type oxidizer, 4) a small amount of soluble metal-ion oxidizer/polishing accelerator, a metal-ion polishing accelerator bound to particles such as to abrasive particles, or both; and 5) at least one of the group selected from a) a small amount of a chelator, b) a small amount of a dihydroxy enolic compound, and c) a small amount of an organic accelerator. Ascorbic acid in an amount less than 800 ppm, preferably between about 100 ppm and 500 ppm, is the preferred dihydroxy enolic compound. The polishing compositions and processes are useful for substantially all metals and metallic compounds found in integrated circuits, but is particularly useful for tungsten.

Abstract: A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Abstract: A plasma reactor chamber is characterized by performing two steps for each one of plural selected chamber parameters. The first step consists of ramping the level of the one chamber parameter while sampling RF electrical parameters at an RF bias power input to said wafer support pedestal and computing from each sample of said RF electrical parameters the values of the plasma parameters. The second step consists of deducing, from the corresponding chamber parameter data generated in the first step, a single variable function for each of the plural plasma parameters having said one chamber parameter as an independent variable, and constructing combinations of these functions that are three variable functions having each of the chamber parameters as a variable.

Abstract: A method of fabricating microelectromechanical (MEMs) systems and in particular for producing silicon carbide (SiC) MEMs devices with improved mechanical properties. The method comprises reacting a dry etch plasma with a layered microstructure; the layered microstructure having an etch mask, a sacrificial layer and a device layer arranged between the etch mask and the sacrificial layer. The dry etch plasma is introduced into the environment of the layered microstructure such that the device layer is etched anisotropically and the sacrificial layer is etched substantially isotropically. The invention also provides a method for tuning MEMs devices by material de-stressing using an inert gas in the dry etch plasma.

Abstract: On a surface of a semiconductor wafer W, a SiCN film, a SiCOH film, a TEOS film, an antireflection film, and a resist film (ArF resist) as a mask are formed in turn. A via hole is formed by plasma etching the SiCOH film with a predetermined etching gas comprising a mixed gas, for example, CF4/CH2F2/N2/O2 mixed gas (not containing a rare gas such as an Ar gas). Thereby, the selection ratio between a low dielectric constant insulation film comprising a carbon containing silicon oxide and the resist can be improved. And at the same time, even when the hole has a minute diameter and a high aspect ratio, an inner wall surface of the hole can be formed in a satisfactory state.

Abstract: The present invention relates to a method of forming an etching mask. According to the present invention, there is provided a method of forming an etching mask, comprising the steps of: depositing a hard mask film containing silicon on a substrate; depositing a photoresist on the hard mask film; patterning the photoresist; and etching the hard mask film using the photoresist pattern as an mask and using an etching gas including a CHxFy(x, y=1, 2, 3) gas. At this time, an etch selectivity of the hard mask film to the photoresist pattern can be increased using a mixed gas including CH2F2 and H2 gases when etching the hard mask film under the photoresist pattern used in a wavelength of 193 nm or less.

Abstract: A method for manufacturing a semiconductor device is provided, which includes depositing a conductive film above an insulating film formed above a semiconductor substrate and having a recess, thereby forming a treating film, polishing the treating film while feeding a first chemical solution containing abrasive particles and a second chemical solution containing an oxidizing agent over a polishing pad, the treating film being contacted with the polishing pad at a first load, and subsequent to the polishing, subjecting a surface of the treating film to a chemical-polishing by continuing the feeding of the first chemical solution over the polishing pad while suspending the feeding of the second chemical solution, the treating film being contacted with the polishing pad at a second load which is smaller than the first load.

Abstract: To protect the structural layers from being eroded in the etching process, a protection layer is deposited on the exposed structural layers of the micromirror. The protection layer is deposited before etching and removed after etching.