Abstract: A manufacturing method for a semiconductor device, includes: preparing a semiconductor wafer having an active surface and a rear surface; forming a plurality of semiconductor regions, each of which having semiconductor elements formed on the active surface of the semiconductor wafer; forming cutting regions on the outer periphery of the semiconductor regions on the active surface of the semiconductor wafer; forming, on the cutting region, a first groove which does not penetrate the semiconductor wafer; forming, on the rear surface of the semiconductor wafer, a second groove which does not penetrate to the first groove in the position corresponding to the cutting region; decreasing a thickness of the semiconductor wafer, connecting the first groove and the second groove, and dividing each of the semiconductor regions from the semiconductor wafer by executing isotropic etching to the rear surface of the semiconductor wafer; and obtaining a plurality of individual semiconductor devices.

Abstract: A method for controlling an etch process comprises providing a wafer having at least a first layer and a second layer formed over the first layer. The thickness of the second layer is measured. An etch selectivity parameter is determined based on the measured thickness of the second layer. An operating recipe of an etch tool is modified based on the etch selectivity parameter. A processing line includes an etch tool, a first metrology tool, and a process controller. The etch tool is adapted to etch a plurality of wafers based on an operating recipe, each wafer having at least a first layer and a second layer formed over the first layer. The first metrology tool is adapted to measure a pre-etch thickness of the second layer. The process controller is adapted to determine an etch selectivity parameter based on the measured pre-etch thickness of the second layer and modify the operating recipe of the etch tool based on the etch selectivity parameter.

Abstract: A method of manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a first insulating film on a substrate that is provided with a structure; forming a second insulating film on the first insulating film; polishing at least the second insulating film; forming a third insulating film on the polished second insulating film; and etching a remaining film including at least the second insulating film or the third insulating film so that an exposed surface of the second insulating film and the third insulating film is parallel with a surface of the substrate.

Abstract: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness effects, the mask layer is treated with a hydrocarbon chemistry or hydrofluorocarbon chemistry or fluorocarbon chemistry or combination of two or more thereof prior to proceeding with the etching process.

Abstract: A structure and method for fabricating a top strap in a magnetic random access memory, MRAM, comprising a damascene process forming a trench in a dielectric layer and resulting in a metal conductor clad on three sides by an inverted U-shape trench liner and cap made up of three layers consisting of a stack of a ferromagnetic material sandwiched between two layers of a refractory metal or an alloy of a refractory metal. First the two sidewalls of the trench are formed with the cladding layer, followed by filling the trench with the metal conductor. In preparing the structure for the capping layer, the metal conductor is recessed with an etch that is selective to the metal conductor over the sidewall stack. This preparation may be performed on selected metal filled trenches and blocked on others, such that after a final polishing step, only those metal conductors that received the recess operation will have the capping layer.

Abstract: A method of fabricating nano-tips involves placing a precursor nanotip with an apex and shank in a vacuum chamber; optionally applying an electric field to the precursor nanotip to remove oxide and other contaminant species; subsequently admitting an etchant gas to the vacuum chamber to perform field assisted etching by preferential adsorption of the etchant gas on the shank; and gradually reducing the applied electric field to confine the adsorption of the etchant gas to the shank as etching progresses.

Abstract: An object to be processed has a structure having an SiC film and an organic Si-low dielectric constant film formed on the SiC film. The SiC film is etched using a plasma produced from an etching gas and using the organic Si low-dielectric constant film as a mask. The etching gas contains CH2F2 or CH3F.

Abstract: A method for manufacturing a self aligned narrow structure over a wider structure based on mask trimming. A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. A patch of memory material is formed on the top surface of the electrode layer across the insulating member for each memory cell to be formed. The patch and the first and second electrodes are formed using a self-aligned process based on mask trimming.

Abstract: It is an object of the present invention to a method for manufacturing a semiconductor device, by which a reaction product formed when a conductive layer is etched can be removed. A method for manufacturing a semiconductor device according to the present invention includes a step of felling a reaction product adhering to a conductive layer so as to extend in a perpendicular direction so that the thickness of the reaction product with respect to a direction in which an active species excited by plasma discharge is accelerated. It is to be noted that the reaction product is produced when the conductive layer is etched.

Abstract: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask, the method includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be exposed to a light source in accordance with a predetermined pattern, depositing an optically writable carbon-containing mask layer on the substrate by (a) introducing a carbon-containing process gas into the chamber, (b) generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, (c) coupling RF plasma bias power or bias voltage to the workpiece.

Abstract: The invention generally relates to compositions and methods for chemically mechanically polishing a substrate, including a polishing accelerator, which is normally one or more oxidizers, an abrasive material, and chelating particles and/or metal-absorbent clay material. In addition, the invention can also involve methods of forming chelator particles and methods of separating metal-containing ions from polishing and/or etching solutions after polishing and/or etching.

Abstract: A chemical mechanical polishing slurry and method for using the slurry for polishing copper, barrier material and dielectric material that includes a first and second slurry. The first slurry has a high removal rate on copper and a low removal rate on barrier material. The second slurry has a high removal rate on barrier material and a low removal rate on copper and dielectric material. The first and second slurries can include silica particles, an oxidizing agent, a corrosion inhibitor, and a cleaning agent.

Abstract: A method for forming patterns which are aligned on either side of a thin film deposited on a substrate. The method includes depositing a first pattern layer on the thin film which may occur before or after the local etching of the thin film to form a first marking. The method includes etching the first pattern layer in order to form a first pattern and depositing a first bonding layer for covering the first marking and the first pattern. The method may include suppressing the substrate as well as etching the first bonding layer to form a second marking at the location of the first marking. The method includes depositing a second pattern layer, and etching the second pattern layer to form the second pattern.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: Disclosed is a CMP slurry comprising a Cu oxidizing agent, a complexing agent for forming a Cu organic complex, a surfactant, an inorganic particle, and a resin particle containing polystyrene, having on the surface thereof a functional group of the same kind of polarity as that of the inorganic particle and having an average particle diameter of less than 100 nm, the resin particle being incorporated at a concentration of less than 1% by weight.

Abstract: Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an etchant, and, consequently, the amount of etched material is limited by the amount of adsorbed first reactant. By repeating steps (a) and (b), controlled atomic-scale etching of material is achieved. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where removal of one or multiple atomic layers of material is desired.

Abstract: The disclosure relates to a process including depositing an imprintable layer on a substrate. The imprintable layer is imprinted into the pattern of an imprint-fabricated ribbon. The pattern from the imprintable layer is transferred to the substrate to be used to fabricate the imprint-fabricated ribbon.

Abstract: Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.

Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate to cover the scan lines, the data lines and the active devices. Then, a plasma treatment is performed to the surface of the organic material layer to form a number of concave patterns. The dimension of each of the concave patterns is smaller than one micrometer. Afterward, pixel electrodes are formed on the organic material layer and each of the pixel electrodes is electrically connected to one of the corresponding active devices.