Abstract: A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region.

Abstract: A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.

Abstract: A method for processing a substrate in a plasma processing chamber. The substrate is disposed above a chuck and surrounded by an edge ring while the edge ring being electrically isolated from the chuck. The method includes providing RF power to the chuck and providing a edge ring DC voltage control arrangement. The edge ring DC voltage control arrangement is coupled to the edge ring to provide first voltage to the edge ring, with the edge ring potential being one of a positive potential, a negative potential and a ground. The method further includes generating a plasma within the plasma processing chamber to process the substrate. The substrate is processed while the edge ring DC voltage control arrangement is configured to cause the edge ring potential to be less than a DC potential of the substrate in an embodiment and to be substantially equal to the DC potential of the substrate in another embodiment.

Abstract: A method for manufacturing a semiconductor device or a semiconductor wafer using a chucking unit is provided to remove a slurry that adheres to the back surface of the semiconductor wafer. An edge portion of a semiconductor wafer is polished while a back surface of the semiconductor wafer is chucked to a chucking unit of a first polishing unit. The polished semiconductor wafer is then dechucked from the chucking unit of the first polishing unit. Next, a gap is formed above the chucking unit of the second polishing unit, and the semiconductor wafer is disposed therein. Water is discharged from the chucking unit of the second polishing unit to clean the back surface of the semiconductor wafer W. Thereafter, the back surface of the semiconductor wafer is chucked to the chucking unit of the second polishing unit, and the semiconductor wafer is polished.

Abstract: A polishing composition contains a deterioration inhibitor for inhibiting deterioration of polishing capability of the polishing composition, an abrasive, and water. The deterioration inhibitor is at least one selected from polysaccharide and polyvinyl alcohol. The polysaccharide is starch, amylopectin, glycogen, cellulose, pectin, hemicellulose, pullulan, or elsinan. Among them, pullulan is preferable. The abrasive is at least one selected from aluminum oxide and silicon dioxide, preferably at least one selected from fumed silica, fumed alumina, and colloidal silica. The polishing composition can be suitably used in polishing for forming wiring a semiconductor device.

Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.

Abstract: Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece processing site configured to receive a microfeature workpiece and a main inlet through which a processing fluid can flow into the processing chamber. The system further comprises a plate in the processing chamber between the main inlet and the workpiece processing site. The plate has a first side generally facing the main inlet and a second side opposite the first side. The plate further includes a plurality of passageways extending from the first side of the plate to the second side. The individual passageways include an inlet portion projecting from the first side of the plate by a separation distance.

Abstract: A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling.

Abstract: Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).

Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.

Abstract: A method for etching a substrate is described wherein a substrate is positioned in a solution of solvent and the substrate is exposed to excitation energy. The method may be applied to the production of thermocouple devices wherein the substrate is poly-ethylene-terephthalate.

Abstract: The invention provides a chemical-mechanical polishing composition comprising a cationic abrasive, a cationic polymer, an inorganic halide salt, and an aqueous carrier. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition. The polishing composition exhibits selectivity for removal of silicon nitride over removal of silicon oxide and polysilicon.

Abstract: A process and system for anisoptropically dry etching through a doped silicon layer is described. The process chemistry comprises SF6 and a fluorocarbon gas. For example, the fluorocarbon gas can include CxFy, where x and y are integers greater than or equal to unity, for example, C4F8.

Abstract: A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.

Abstract: Particles adhering to the surface of a substrate are removed by physical action of injection of droplets or megasonic vibrations or by combination of the physical action and slight etching on the surface of the substrate. On the other hand, metal contaminants adhering to the surface of the substrate are altered to hydroxides with an alkaline solution and thereafter dissolved with an acid solution to be removed. Thus, it is possible to rapidly process the substrate while minimizing the quantity of etching on the surface of the substrate.

Abstract: The surface topology of a plug surface area-containing surface of a semiconductor device can be improved by removing material to create a first planarized surface with at least one plug surface area, typically a tungsten or copper plug area, comprising a recessed region. A material is deposited onto the first planarized surface, to create a material layer, and into the upper portion of the recessed region. The material layer is removed to create a second planarized surface with the material maintained in the upper portion of the recessed region. To form a semiconductor phase change memory device, a phase change element is formed between the at least one plug area, acting as a first electrode, at the second planarized surface and a second electrode.

Abstract: A plasma reactor chamber is characterized by performing the following steps: (a) for each one of the chamber parameters, ramping the level of the one chamber parameter while sampling RF electrical parameters at an RF bias power input to the wafer support pedestal and computing from each sample of the RF electrical parameters the values of the plasma parameters, and storing the values with the corresponding levels of the one chamber parameter as corresponding chamber parameter data; (b) for each one of the chamber parameters, deducing, from the corresponding chamber parameter data, a single variable function for each of the plasma parameters having the one chamber parameter as an independent variable.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: An object to be process has a structure having an SiC film 61 and an organic Si-low dielectric constant film 62 formed on the SiC film 61. The SiC film 61 is etched using a plasma produced from an etching gas and using the organic Si low-dielectric constant film 62 as a mask. The etching gas contains CH2F2 or CH3F.

Abstract: The present polishing slurry is a polishing slurry for chemically mechanically polishing a surface of a GaxIn1?xAsyP1?y crystal (0?x?1, 0?y?1), characterized in that this polishing slurry contains abrasive grains formed of SiO2, this abrasive grain is a secondary particle in which a primary particle is associated, and a ratio d2/d1 of an average particle diameter d2 of a secondary particle to an average particle diameter d1 of a primary particle is not less than 1.6 and not more than 10. According to such the polishing slurry, a crystal surface having a small surface roughness can be formed on a GaxIn1?xAsyP1?y crystal at a high polishing rate and effectively.