Abstract: A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the amorphous carbon organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the amorphous carbon organic hardmask with the plasma, with the amorphous carbon organic hardmask being at a temperature in excess of 200° C., to remove the amorphous carbon organic hardmask without substantially harming the underlying substrate.

Abstract: A continuous in situ process of deposition, etching, and deposition is provided for forming a film on a substrate using a plasma process. The etch-back may be performed without separate plasma activation of the etchant gas. The sequence of deposition, etching, and deposition permits features with high aspect ratios to be filled, while the continuity of the process results in improved uniformity.

Abstract: To smooth silicon sliders that have been parted from each other on a wafer by DRIE, an isotropic etch using fluorine either in a gas or in an aqueous solution is performed prior to separating the individual sliders from the wafer.

Abstract: A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.

Abstract: A method of manufacturing a tunable wavelength optical filter. The method includes steps of forming a first sacrificial oxide film for floating a lower mirror on a semiconductor substrate; sequentially laminating conductive silicon films and oxide films for defining a mirror region on the first sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form a lower mirror; sequentially laminating conductive silicon films and oxide films for defining the mirror region on a second sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form an upper mirror and forming an optical tuning space between the lower mirror and the upper mirror and etching the first sacrificial oxide film and the second sacrificial oxide film such that the lower mirror is floated on the semiconductor substrate.

Abstract: The present invention relates to a self-aligning patterning method which can be used to manufacture a plurality of multi-layer thin film transistors on a substrate. The method comprises firstly forming a patterned mask 20 on the surface of a sacrificial layer 18 which is part of a multi-layer structure 10 which comprises the substrate 12, a conductive layer 14, an insulating layer 16 and the sacrificial layer 18. Unpatterned areas are then etched to remove the corresponding areas of the sacrificial layer, the insulating layer 16 and the conductive layer 14 thereby leaving voids. A layer of dielectric 22 is then deposited over the etched multi-layer structure to at least substantially fill the voids. The deposited dielectric is then etched in order to at least partially expose the sides of the remaining areas 28 of the sacrificial layer. Conductive material 30 is then deposited on the surface of the etched dielectric.

Abstract: A method of manufacturing a flash memory device which an etch-prevention layer, first and second interlayer insulating layers, and first, second and third hard mask layers are sequentially formed on a semiconductor substrate. The third hard mask layer is etched to expose a portion of a region on the second hard mask layer. A photoresist pattern of a line shape is formed on the entire surface such that the photoresist pattern is exposed to be narrower than the region through which the second hard mask layer is exposed. The second hard mask layer is etched using the photoresist pattern as a mask. The first hard mask layer is etched using the photoresist pattern as a mask, and the second and first interlayer insulating layers are then etched using the remaining third and second hard mask layers as masks, thus forming a drain contact hole having a square shape.

Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.

Abstract: A method of producing a semiconductor device is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.

Abstract: A manufacturing method of a mask blank from which an unnecessary resist film formed on the peripheral edge of a substrate main surface is removed in a mask blank, which is an original substrate of a transfer mask having a transfer pattern for transferring to a body to be transferred on a substrate, and a manufacturing method of a transfer mask using the mask blank.

Abstract: The invention is directed to a method and composition for providing roughened copper surfaces suitable for subsequent multilayer lamination. A smooth copper surface is contacted with an adhesion promoting composition under conditions effective to provide a roughened copper surface, the adhesion promoting composition consisting essentially of an oxidizer, a pH adjuster, a topography modifier, and a uniformity enhancer. A coating promoter may be used in place of the uniformity enhancer or in addition to the uniformity enhancer. The adhesion promoting composition does not require a surfactant. The process may further comprise the step of contacting the uniform roughened copper surface with a post-dip, wherein the post-dip comprises an azole or silane compound or a combination of said azole and said silane. The post-dip may further comprise, alone or in combination, a titanate, zirconate, and an aluminate. The pH adjuster is preferably sulfuric acid and the oxidizer is preferably hydrogen peroxide.

Abstract: A method for forming a via hole and a trench for a dual damascene interconnection comprises forming a via hole through an inter-metal insulating film to expose a portion of a surface of an etch stop film on a lower metal film, forming a photoresist film on an entire surface of the resultant structure and in the via hole, exposing a top surface and a side surface of the inter-metal insulating film by recessing the photoresist film using a development process for the photoresist film, forming a bottom antireflective coating film on the exposed surfaces of the inter-metal insulating film and the photoresist film, forming a mask pattern on the bottom antireflective coating film, forming a trench by an etching process using the mask pattern as an etch mask, and completely removing the photoresist film within the via hole.

Abstract: In an operation status determination method for a plasma processing apparatus, a principal component analysis is carried out by using operation status data groups. Processing parameter values in the respective operation status data groups are converted into principal component scores which are plotted in a two-dimensional coordinate system with axes of the selected principal components. A movement vector P from a first recipe operation status data group for reference apparatus to a first recipe operation status data group for target apparatus is calculated. An actually measured normal area A2 is set, and a predicted normal area B2 is set by moving the area A2 along the movement vector P. Then, it is determined whether or not the principal component scores corresponding to the respective processing parameter values when the second recipe is applied to the target apparatus are included in the predicted normal area B2.

Abstract: A method for etching features into a dielectric layer over a substrate and existent below a polymeric hard mask is provided. The substrate is placed in a plasma processing chamber. Mask features are etched into the polymeric hard mask and necks are formed inadvertently. A plasma treatment process performed before the dielectric etch step process can selectively etch away the necks. As a result, neckless features are created into the polymeric hardmask. Features etched into the underneath dielectric layer through the neckless polymeric hard mask have straight profiles.

Abstract: An objective of the present invention is to provide a polishing pad for a semiconductor wafer and a laminated body for polishing of a semiconductor wafer equipped with the same which can perform optical endpoints detection without lowering the polishing performance as well as methods for polishing of a semiconductor wafer using them. The polishing pad of the present invention comprises a substrate 11 for a polishing pad provided with a through hole penetrating from surface to back, a light transmitting part 12 fitted in the through hole, the light transmitting part comprises a water-insoluble matrix material (1,2-polybutadiene) and a water-soluble particle (?-cyclodextrin) dispersed in the water-insoluble matrix material, and the water-soluble particle is less than 5% by volume based on 100% by volume of the total amount of the water-insoluble matrix material and the water-soluble particle.

Abstract: In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate.

Abstract: A selective dry etch process includes use of an etchant that includes C2HxFy, where x is an integer from three to five, inclusive, where y is an integer from one to three, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.

Abstract: According to one embodiment, a method for manufacturing a substrate for a discrete track recording media, the method includes forming an imprint resist layer on a substrate, imprinting, on the imprint resist layer, a stamper formed with patterns of protrusions and recesses corresponding to recording track zones and servo zones to transfer the patterns of protrusions and recesses to the imprint resist layer, removing the stamper from the imprint resist layer, and diffusing liquefied CO2 in a process chamber set at a pressure of 2 to 5 atm, diffusing liquefied H2O in the process chamber set at a pressure of 0.01 to 1 atm, or diffusing a reactive gas selected from a group consisting of liquefied CF4, CHF3, SF6, and C2F6 in the process chamber set at an arbitrary pressure, to jet spray the liquefied gas onto a surface of the substrate.

Abstract: Microbolometers with regionally thinned microbridges are produced by depositing a thin film (0.6 ?m) of silicon nitride on a silicon substrate, forming microbridges on the substrate, etching the thin film to define windows in a pixel area, thinning the windows, releasing the silicon nitride, depositing a conductive YBaCuO film on the bridges, depositing a conductive film (Au) on the YBaCuO film, and removing selected areas of the YBaCuO and conductive films.

Abstract: Methods of performing controllable lateral etches into the silicon layer using a plasma-enhanced etch-deposit-etch sequence are disclosed. The first etch step etches into the silicon layer. The deposition step passivates horizontal surfaces, including the bottom of the etched feature. The second etch step increases the lateral undercut, resulting in a low V:L ratio silicon layer etch.