Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks for storing data and each block includes a plurality of pages. The controller is configured to convert a host read command into a read-operation instruction to the flash memory to perform a default read operation to read page data from the flash memory. The default read operation has a default read threshold voltage. In response to a failure of the default read operation, the controller is configured to sequentially perform a read operation on the flash memory using a read threshold voltage with respect to each entry of a plurality of entries in a read-retry table, and replace the default read threshold voltage with the read threshold voltage corresponding to the read operation being successfully performed.

Abstract: An information processing circuitry includes a storage data generation circuitry, a storage circuitry, a comparison data generation circuitry, and a data comparison circuitry. The storage data generation circuitry is configured to add redundancy bits and a write flag indicating that writing has been made, to input data to generate storage data. The storage circuitry is configured to store the storage data. The comparison data generation circuitry is configured to generate redundancy bits from data stored in the storage circuitry and address accessing to the storage circuitry. The data comparison circuitry is configured to compare the redundancy bits added by the storage data generation circuitry with the redundancy bits generated by the comparison data generation circuitry to execute error detection based on a comparison result and on the write flag.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a data region and a parity region. The I/O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit generates control signals by decoding a command received from a memory controller. The ECC engine is configured to a first parity data based on a first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing to write the first parity data in the parity region based on a receiving timing of a second command successive to the first command and a reference time interval.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) sending a set of data access requests regarding a set of encoded data slices to slice routers of the DSN. The method continues by a first slice router identifying a first storage unit of a first storage unit group based on a first slice name of a set of corresponding slice names that includes a first pillar number, wherein the first slice router is responsible for processing access requests that include the first pillar number. The method continues by the first slice router sending a first data access request of the set of data access requests to the first storage unit. The method continues by the first slice router receiving a first data access response. The method continues by the first slice router forwarding the first data access response to the DS processing unit.

Abstract: A data accessing method using data protection with aid of a parity check matrix having partial sequential information, and associated apparatus such as memory device, memory controller, and decoding circuit thereof are provided. The data accessing method may include: in response to a read request, starting receiving protected data corresponding to the read request from predetermined storage space; generating the parity check matrix; performing syndrome calculation based on the parity check matrix according to a codeword to generate and output a syndrome for the codeword; performing error detection according to the syndrome to generate and output a decoding result signal, and performing error location decoding according to the syndrome to generate and output an error location; performing error correction of the codeword, to correct an error at the error location of the codeword; and performing further processing according to the one or more codewords obtained from the protected data.

Abstract: Various embodiments relate to a method and system for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error detection code (EDC), that can detect up to 4 bit errors, as first encoded data; determining the Hamming weight of the first encoded data; inverting the determined Hamming weight; concatenating the first encoded data and three copies of the inverted Hamming weight as concatenated data; encoding the concatenated data with an error correcting code (ECC), that can correct 1 bit error, as second encoded data; and storing the second encoded data in the memory.

Abstract: This application provides a data processing method and a communications device. The data processing method includes: determining, by a first communications device, NCB, based on a size of the circular buffer of the communications device and an information processing capability of a second communications device; and obtaining, by the first communications device, a second encoded bit segment from a first encoded bit segment having a length of NCB. According to the data processing method and the communications device provided in this application, decoding complexity of the communications device can be reduced and communication reliability can be improved.

Abstract: An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.

Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.

Abstract: An example system comprises: a master bus electrically coupled to a master multiplexer controlled by a test mode signal selecting between a master physical interface (PHY) and a slave bus of a plurality of slave buses, wherein each slave bus is electrically coupled to a respective slave multiplexer controlled by the test mode signal selecting between a respective slave PHY and the master bus; a plurality of memory components, wherein each memory component of the plurality of memory components is electrically coupled to one of: the master bus or a slave bus of the plurality of slave buses; and a memory test interface electrically coupled to the master bus.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.

Abstract: A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns. The array includes a plurality of word lines, first bit lines and second bit lines, a NOR gate per column Each word line activates memory cells in a row and thereby establishes an activated row. First bit lines and second bit lines connect memory cells in columns, each first bit line provides the result of a Boolean AND operation between data stored in the first activated row and data stored in the second activated row. Each second bit line provides the result of a Boolean NOR operation between data stored in the first activated row and data stored in the second activated row. Each per-column NOR gate is connected to the first and second bit lines of each column and compares data stored in the first activated row with data stored in the second activated row.

Abstract: A memory controller for controlling a memory device including a register for storing a plurality of parameters includes: a register information storage configured to store the plurality of parameters as a plurality of setting parameters, a register controller configured to provide the memory device with a parameter change command for requesting a selected parameter to be changed to a set value, and acquire, from the memory device, Cyclic Redundancy Check (CRC) calculation information on the plurality of parameters including the selected parameter, a CRC reference information generator configured to generate CRC reference information on the plurality of setting parameters including at least one setting parameter changed to the set value, and a CRC information comparator configured to determine whether an error is included in the plurality of parameters according to a comparison result between the CRC calculation information and the CRC reference information.

Abstract: Embodiments provide a polar code encoding and decoding method in a communications system. Under the method, a basic quantized sequence can be obtained. The basic quantized sequence includes a quantized value used to represent reliability corresponding to a polarized subchannel. A target quantized sequence based on the basic quantized sequence can also be obtained. A relative magnitude relationship between elements in the target quantized sequence is nested with a relative magnitude relationship between elements in the basic quantized sequence. K largest quantized values in the target quantized sequence can be determined based on a non-fixed bit length K and polarized subchannels corresponding to the K largest quantized values can be used as a non-fixed bit position set. Polar code encoding or decoding can be performed based on the non-fixed bit position set.

Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.

Abstract: According to certain embodiments, a transmit node in a wireless communications system includes a first universal rate-compatible polar encoder and a transmitter. The first universal rate-compatible polar encoder is configured for a family of two or more types of channels and encodes a plurality of information bits to provide a plurality of coded bits. The transmitter transmits the plurality of coded bits to a receive node.

Abstract: An information handling system includes a processor and memory devices that each include a voltage regulator configured to be enabled by a command from the processor. The processor boots the information handling system, including providing the command to the memory devices, and detects that one of the memory devices failed to boot. The processor determines that it is unknown whether the failing memory device is the first memory device or the second memory device. In response, the processor determines which one of the memory devices failed to boot, by rebooting the information handling system, providing a command to a selected one of the memory devices, and determining whether or not the selected one of the memory devices failed to boot.

Abstract: Disclosed are devices, systems and methods for improved decoding of a binary linear code. An example method includes receiving a noisy codeword; computing a syndrome based on the noisy codeword; identifying N error patterns that correspond to the syndrome; selecting M error patterns from the N error patterns, wherein M?N are positive integers, wherein a distance between a codeword corresponding to each of the M error patterns and the noisy codeword is less than a distance between a codeword corresponding to any other error pattern and the noisy codeword, and wherein the distance excludes a Hamming distance; modifying the noisy codeword based on each of the M error patterns one-at-a-time; and decoding the modified noisy codeword one-at-a-time until a successful decoding is achieved.

Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.