Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, detect an uncorrectable error in the user data, detect a sector balanced when the number of 1's and 0's in the user data is within the difference stored in a range register, apply an XOR RAID recovery to correct the uncorrectable error in the user data; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to forego an additional read of a sector N with a different value of the read threshold when the sector balanced initiates the XOR RAID recovery.

Abstract: Example polar coding methods and apparatus are described. One example method includes determining a sequence used to code to-be-coded bits. Polar coding is performed on the to-be-coded bits by using the sequence to obtain coded bits. The sequence is used to represent a reliability order of N polarized channels, N is a mother code length of a polar code, and N is a positive integer power of 2.

Abstract: A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.

Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Abstract: A TTCN-based test system for testing test-cases is provided. The test system includes a test executable which includes a compiled TTCN code. A simulated device under test (DUT) includes a pre-recorded log-file which describes at least partially the behavior of the simulated DUT. A test runtime interface is provided between the test executable and the simulated DUT. A test computer (PC) is configured to perform the testing by executing the compiled TTCN code and by exchanging via the test runtime interface protocol messages with the simulated DUT during the execution of the compiled TTCN code. A TTCN-based test method for testing test-cases and a non-transitory computer-readable recording medium is also provided.

Abstract: A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: Provided is an encoding method and device and a decoding method and device for structured LDPC. The encoding method includes: determining a base matrix used for encoding and performing an LDPC encoding operation on a source information bit sequence according to the base matrix and an expansion factor Z corresponding to the base matrix to obtain a codeword sequence, where Z is a positive integer. The base matrix includes multiple submatrices and the submatrices include an upper-left submatrix Hb1 and an upper-left submatrix Hb2, and the upper-left submatrix Hb1 is an upper-left submatrix of the upper-left submatrix Hb2.

Abstract: The subject matter described herein is directed towards a technology that increases the reliability of transmitting information, and extends the coverage of a vehicle-to-everything (V2X) network by propagating received information in a multiple-stage chain communication in a wireless communication system. A transmitting device transmits a communication message with repetition data indicating number of times the communication message is to be retransmitted in the wireless communication system. A receiving device determines from the repetition data that the communication message is intended to be retransmitted, modifies (e.g., decrements) the repetition data, and retransmits the communication message in association with the modified repetition data.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a repeater configured to repeat, in the LDPC codeword, at least some bits of the LDPC codeword in the LDPC codeword so that the repeated bits are to be transmitted in the current frame; a puncturer configured to puncture some of the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits, and generate additional parity bits to be transmitted in a previous frame of the current frame.

Abstract: A memory device includes: an in-memory error correction code generating circuit suitable for generating an in-memory error correction code based on a data received from a memory controller during a write operation; a memory core suitable for storing the received data and the in-memory error correction code during the write operation; an in-memory error correction circuit suitable for correcting an error of the data which is read from the memory core based on the in-memory error correction code which is read from the memory core during a read operation; and a data transmitter suitable for transferring the data whose error is corrected by the in-memory error correction circuit to the memory controller during the read operation, and transferring the data which is read from the memory core to the memory controller during a read retry operation.

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: A RAID system, RAID controller, method, and computer program product for reducing the number of reads of XOR data in a multi-storage-enclosure RAID array includes a RAID array controller that implements a selected distributed RAID scheme. The RAID array controller determines a set of drives and logical block addresses corresponding to a parity group and divides the set of drives into subsets of drives that are located within each individual storage enclosure of the multiple storage enclosures. The controller issues a single EnclosureXOR Read to each storage enclosure corresponding to the subsets of drives to read enclosure-level intermediate XOR data calculated by each storage enclosure for each subset of drives and in response to receiving the enclosure-level intermediate XOR data results from all storage drives in the parity group, and calculates an array level XOR result by XORing the enclosure-level intermediate XOR data results from the storage enclosures.

Abstract: The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.

Abstract: A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.

Abstract: Systems and methods are disclosed for performing hybrid automatic repeat request (HARQ) for grant-free uplink transmissions. Some of the systems and methods disclosed herein may address problems such as how to perform acknowledgement (ACK) and/or negative acknowledgement (NACK), how to determine and signal retransmission timing, how to determine the transmission/retransmission attempt and the redundancy version (RV), and/or how to perform the HARQ combining.

Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.

Abstract: A storage device may include a decoder configured to connect bits to a content node based on content-aware decoding process. The content-aware decoding process may be dynamic and determine connection structures of bits and content nodes based on patterns in data. In some cases, the decoder may connect non-adjacent bits to a content node based on a content-aware decoding process. In other cases, the decoder may connect a first number of bits to a first content node and a second number of bits to a second content node. In such cases, the first number of bits and the second number of bits are a different number.

Abstract: An apparatus for providing fault resilience has storage for providing a plurality of compare data blocks, and processing circuitry that performs, for each compare data block, a processing operation using the input data and the compare data block to produce a match condition indication for that compare data block. Performance of the processing operation for each compare data block should result in only one match condition indication indicating a match. Evaluation circuitry evaluates the match condition indications produced for the plurality of compare data blocks and is arranged, in the presence of only one match condition indication indicating a match, to perform a false hit check procedure in order to check for presence of a false hit. In the presence of the false hit, the evaluation circuitry produces an error indication as the outcome indication, but otherwise produces a hit indication as the outcome indication.