Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving an access request via a network. A set of possible storage units for performance of the access request are determined. A latency summarization value is determined for each of the set of possible storage units based on historical latency data for the set of possible storage units. A weight for each of the set of possible storage units is determined based on the latency summarization values to generate a plurality of weights. A probabilistic selection function is performed in accordance with the plurality of weights to select a proper subset of the set of possible storage units. A plurality of requests are generated based on the access request for transmission, via the network, to the proper subset of the set of possible storage units.

Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.

Abstract: A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode.

Abstract: Described herein is a system and method for coded streaming data to facilitate recovery from failed or slow processor(s). A batch of processing stream data can be partitioned into a plurality of data chunks. Parity chunk(s) for the plurality of data chunks. The plurality of data chunks and the parity chunk(s) can be provided to processors for processing. Processed data of at least some (e.g., one or more) of the plurality of data chunks, and, processed data of parity chunk(s) are received. When it is determined that processed data for a pre-defined quantity of data chunks has not been received by a pre-defined period of time, the processed data for particular data chunk(s) of particular processor(s) from which processed data has not been received are determined based, at least in part, upon the received processed parity chunk(s) and the received processed data chunk(s).

Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

Abstract: This application provides a coding method and apparatus, and a device. The method includes: dividing, by a sending device, a subchannel location sequence number set into at least two mutually exclusive subsets based on an interleaving operation, where a subchannel location in each subset still belongs to the subset and does not belong to another subset after any quantity of interleaving operations are performed; determining, by the sending device, an information bit location set and a frozen bit location set of a to-be-coded polar polar code based on the at least two mutually exclusive subsets; and coding, by the sending device, the to-be-coded polar code based on the information bit location set and the frozen bit location set. The coding method and apparatus, and the device provided in this application can improve communication performance of polar coding.

Abstract: Provided herein may be a memory controller and a method of operating the memory controller. The memory controller may control a memory device that stores data, and may include a bit counter configured to generate a count value by counting any one of bits in a programmed state and an erased state contained in the data, a flash translation layer configured to generate page information indicating an address of the data stored in the memory device, an additional data generator configured to generate judgment data for determining whether the data has changed, based on the count value and the page information, a comparator configured to generate comparison information by comparing the judgment data with detection data generated based on data read from the memory device, and a read data controller configured to perform an operation of correcting an error in the read data based on the comparison information.

Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rater is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Abstract: A method includes, upon a read operation for a stripe of a storage device, determining a percentage amount of potential read amplification for the read operation. A current age of the stripe in the read operation is determined as a percentage of a longest safe elapsed time between read scrub operations on a stripe of the storage device. A read scrub operation is performed on the stripe when the current age is greater than the percentage amount of potential read amplification.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Abstract: Apparatus and methods are provided for polar code sub-block interleaving and bit selection. In one novel aspect, middle-part interlaced sub-block interleaving is provided for polar code interleaving. In one embodiment, the middle part of the polar code is interlaced and generates the interleaved polar code. In another embodiment, the lower part and the upper part are also sub-block interleaved with the middle-part interlaced method. In another novel, rate-dependent unified bit selection is provided. The bit selection is categorized into three operation categories of repetition, puncturing and the shortening. Each category follows unified bit selection rule with different categories differ only in the access scheme. In one embodiment, the circular buffer is used for bit selection.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving an access request via a network. A set of possible storage units for performance of the access request are determined. A latency summarization value is determined for each of the set of possible storage units based on historical latency data for the set of possible storage units. A weight for each of the set of possible storage units is determined based on the latency summarization values to generate a plurality of weights. A probabilistic selection function is performed in accordance with the plurality of weights to select a proper subset of the set of possible storage units. A plurality of requests are generated based on the access request for transmission, via the network, to the proper subset of the set of possible storage units.

Abstract: A data encoding system includes a non-transitory memory, a processor, a digital-to-analog converter (DAC) and a transmitter. The non-transitory memory stores a predetermined file size threshold. The processor is in operable communication with the memory, and is configured to receive data. The processor detects a file size associated with the data. When the file size is below the predetermined file size threshold, the processor compresses the data using a variable length codeword (VLC) encoder. When the file size is not below the predetermined file size threshold, the processor compresses the data, using a hash table algorithm. The DAC is configured to receive a digital representation of the compressed data from the processor and convert the digital representation of the compressed data into an analog representation of the compressed data. The transmitter is coupled to the DAC and configured to transmit the analog representation of the compressed data.

Abstract: A data storage system performs operations including receiving a data write command specifying data to be written; selecting an irregular LDPC encoding scheme of a plurality of available irregular LDPC encoding schemes available to the encoder in accordance with (i) a working mode of the data storage system, (ii) device-specific criteria and/or (iii) a data type of the specified data; and encoding the specified data to be written using the selected irregular LDPC encoding scheme.

Abstract: Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: A method includes determining whether a tunneling magnetoresistance (TMR) sensor is corroded using resistance, amplitude and signal to noise ratio (SNR) measurements of the sensor. A method to determine whether a TMR sensor is corroded includes determining an expected initial resistance value, RTMRoUse and measuring a resistance value, RTMR, of the sensor. The method includes calculating a ratio of the RTMR value and the expected initial resistance value, RTMRoUse and determining whether the ratio is in a predefined range for the TMR sensor. In response to determining that the ratio of the sensor is within the predefined range, the method includes outputting an indication that the TMR sensor is corroded. In response to determining that the ratio of the sensor is outside the predefined range, the method includes outputting an indication that the TMR sensor is not corroded.