Abstract: Data set groups are determined, wherein each data set group includes a plurality of data sets and each data set includes error-correcting information for content user data of the data set. One or more versions of data set group level error-correcting information for each data set group are calculated. The data set groups on stored a tape storage media. After the data set groups are stored, an amount of storage available on one or more regions of the tape storage media associated with one or more tape edges is identified. An instruction is provided to store at least a partial amount of the calculated one or more versions of data set group level error-correcting information for the data set groups able to be stored in the amount of storage available on the one or more regions of the tape storage media associated with the one or more tape edges.

Abstract: A coding and modulation apparatus and method are presented, particularly for use in a system according to IEEE 802.11. The apparatus comprises an encoder configured to encode input data into cell words according to a low density parity check code, LDPC, and a modulator configured to modulate said cell words into constellation values of a non-uniform constellation and to assign bit combinations to constellation values of the used non-uniform constellation, wherein said modulator is configured to use, based on the total number N of constellation points of the constellation and the code rate R, a particular non-uniform constellation, which has been optimized using the peak-to-average power ratio (PAPR).

Abstract: A communication unit of the present disclosure includes a decoding section configured to decode transfer data transmitted from a communicated unit, by a first method using a first error detecting code, and a second method using at least an error correcting code, and a determination section that performs determination as to whether the transfer data are data in the first method including the first error detecting code or data in the second method including the error correcting code.

Abstract: The disclosure is related to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A method for operating a first device in a wireless communication system includes receiving information bits and distributed cyclic redundancy check (CRC) bits from a second device, and decoding the information bits and the distributed CRC bits, wherein the information bits and the distributed CRC bits are decoded by using a successive cancellation list decoding scheme that uses a parity check matrix determined based on a linear combination of rows of a predetermined parity check matrix, or by using a successive cancellation flip decoding scheme that uses the distributed CRC bits.

Abstract: Systems and methods illustrated herein disclose error correction of a two-dimensional (2D) symbol. The systems and methods include reading, by a hardware processor, a plurality of codewords in the 2D symbol. Further, the systems and methods include identifying, by the hardware processor of, an optically ambiguous codeword of the plurality of codewords in the 2D symbol. The optically ambiguous codeword corresponds to a codeword with a minimum interior contrast level below a predefined minimum interior contrast level. Further, the systems and methods include correcting, by the hardware processor, errors in the optically ambiguous codeword based on, a location of the optically ambiguous codeword and an erroneous decoded value associated with the optically ambiguous codeword.

Abstract: A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.

Abstract: A non-volatile (NV) memory write method using data protection with aid of pre-calculation information rotation, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory write method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through pre-calculation information rotation type encoding, wherein regarding a message: starting encoding a message to calculate a partial parity code according to the message and a transpose matrix of a part-one matrix within a parity check matrix; loading a partial matrix of an inverse matrix of a part-two matrix within the parity check matrix from a storage circuit; applying the partial matrix and its rotated version(s) generated through rotation control to generate and output a corresponding parity code; and writing into the NV memory.

Abstract: The present disclosure relates generally to biometric identification and electrostatic discharge (ESD) test verification system. Embodiments of the present disclosure provide systems and methods that combine ESD testing and biometric identification technology at a work area, such as a manufacturing workstation, to ensure that an employee is uniquely identified, and that the employee's electrical grounding straps are present and functioning correctly. Based on a result of the ESD testing and a biometric identification used to login at an ESD controlled work area, access to one or more functions of the manufacturing workstation may be granted, denied, or otherwise restricted.

Abstract: An example computer-implemented method includes receiving hardware testing results, an address, input/output (I/O) data, a redundancy status, and an input-memory-output mapping corresponding to a memory being tested. The method includes locating a failed cell of the memory based on the hardware testing results, the address, the input/output data, the redundancy status, and the input-memory-output mapping. The method also includes automatically repairing the failed cell.

Abstract: Systems and methods are disclosed for performing hybrid automatic repeat request (HARQ) for grant-free uplink transmissions. Some of the systems and methods disclosed herein may address problems such as how to perform acknowledgement (ACK) and/or negative acknowledgement (NACK), how to determine and signal retransmission timing, how to determine the transmission/retransmission attempt and the redundancy version (RV), and/or how to perform the HARQ combining.

Abstract: A method for checking storage units of flash memory of flash memory device includes: writing data into storage units; and performing data read operation to read data from storage units to compare read data with written data to check whether data is correctly written into storage units, and data read operation includes: performing sequential read operation to sequentially select first storage unit and to read data from first storage unit according to serial order numbers; determining whether first storage unit is damaged; accumulating a number of damaged storage units if first storage unit is damaged; determining whether the number of damaged storage units is larger than first threshold number; and exiting sequential read operation and performing random read operation to read data of specific storage unit if the number of damaged storage units is larger than first threshold number.

Abstract: A system includes a processor configured to determine that transmission data indicates that first data was transmitted via a digital radio channel and that reception data indicates that second data was received via the digital radio channel. The first data is transmitted concurrently with transmission of an analog signal. The processor is configured to detect an error in transmission of the first data based on a comparison of adjacent portions of the first data to non-adjacent portions of the second data. The processor is configured to, in response to detecting the error, initiate display of a default image concurrently with output of an audio signal that is based on the analog signal and to initiate retransmission of the first data to cause second particular data to be output subsequent to the output of the default image. The second particular data corresponds to the retransmitted first data.

Abstract: A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder. The storage section stores a first copy, a second copy and a third copy of a data item in physically separated columns. The comparison section temporarily stores the first copy in a first row and the second copy in a second row. The comparing element compares between bits of the first and second rows and provides at least one per bit change indication. The selective write unit receives at least one per bit change indication and fetches from the third copy a correct value for each bit having a positive bit change indication. The row decoder concurrently writes each correct value back to its bit location in the first and second copies.

Abstract: A semiconductor circuit of the disclosure includes: a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.

Abstract: A semiconductor apparatus includes a storage unit, an ECC decoder, and a selection unit. The storage unit stores data. The ECC decoder can detect and correct an error of a predetermined number of bits in data outputted from the storage unit, and can detect an error equal to or larger than bits larger than the predetermined number of bits in the data. The selection unit selects and outputs one of the data outputted from the ECC decoder and a preset fixed value, in accordance with a detection signal indicating whether or not the error equal to or larger than the bits larger than the predetermined number of bits is detected by the ECC decoder.

Abstract: A test method for testing a built-in memory in a computer device includes the following operations. The built-in memory is tested by a test function of a basic input/output system (BIOS) in the computer device to create a data file. An analysis application is performed by a test device to analyze the data file. According to analyzing the data file, an abnormal memory chip is determined whether to exist in the built-in memory. The data file includes test data of memory chips in the built-in memory.

Abstract: Modern mobile communication systems transfer data by error protection measures including the use of a forward error correction code for the channel coding and a HARQ (hybrid automatic repeat request) system for the repeated transfer of incorrect transport blocks in response to the error protection mechanisms failing. When a turbo code is used as an error protection code, two decoders work on the decoding of the turbo code. Disclosed is an expanded HARQ system wherein the receiving side determines which of the decoders was more greatly challenged in the decoding of the turbo code and reports this to the transmitting side. Instead of uniformly providing more redundancy data to both decoders, more redundancy data are targetedly provided to the more greatly challenged decoder in the expanded HARQ process than in the case of the repetition operation according to the typical HARQ process reducing the latency of the data transfer.

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

Abstract: A method is disclosed comprising encoding a message into blocks, determining a collection of DNA symbols for each of the blocks from the encoded message, performing a second encoding of the determined collection of DNA symbols from the encoded message, detecting a presence of errors in the second encoding and establishing an authentication of each block and further using zero-knowledge protocol to securely authenticate the message without disclosing the actual message.

Abstract: The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 7/16 or 8/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.