Abstract: Devices, computer-readable media, and methods for selecting a type of packet loss protection for a network-based communication based upon a latency estimate are disclosed. For example, a processing system including at least one processor may obtain a latency estimate for a network-based communication, determine whether the latency estimate exceeds a latency threshold for selecting a type of packet loss protection, and select, the type of packet loss protection for the network-based communication from among a first type of packet loss protection and a second type of packet loss protection based upon the determining. When the latency estimate is determined to not exceed the latency threshold, the first type of packet loss protection is selected. When the latency estimate is determined to exceed the latency threshold, the second type of packet loss protection is selected.

Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

Abstract: An embodiment of the present invention discloses a data sending and receiving method. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present invention, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: A network device polar encodes data to obtain a first encoded bit sequence, wherein the first encoded bit sequence comprises: bits in even number locations in the first encoded bit sequence and bits in odd number locations in the first encoded bit sequence; then the device interleaves the first encoded bit sequence to obtain an interleaved bit sequence; finally, the device rate matches the interleaved bit sequence and outputs the bit sequence after rate matched, wherein bits in even number locations of the interleaved bit sequence are from the bits in even number locations of the first encoded bit sequence, bits in odd number locations of the interleaved bit sequence are from the bits in odd number locations of the first encoded bit sequence.

Abstract: A solution is disclosed for using low-density parity check codes in connection with a retransmission scheme. A first apparatus encodes a data bit set by using a first parity check matrix in a low-density parity check encoder. The first apparatus transmits the encoded data bit set and some parity bits of the set to a second apparatus in a message, and determines that the second apparatus was not capable of decoding the data bit set. The first apparatus modifies the first parity check matrix by using an overlapping matrix where overlapping elements of the first parity check matrix and the overlapping matrix are combined into a second parity check matrix. The first apparatus encodes the data bit set by using the second parity check matrix to provide a second parity bit set, and transmits at least some parity bits of the second parity bit set to the second apparatus.

Abstract: Technologies are disclosed for identifying and remediating correctable hardware errors. A firmware can detect a system management interrupt (“SMI”) generated by a hardware device responsive to the occurrence of a correctable error. Once the firmware has identified the device that generated the SMI, the firmware can determine whether an earliest recorded error generated by the identified device is longer ago than a threshold amount of time. If the earliest recorded error generated by the device is not longer ago than the threshold amount of time, the firmware can increment an error count for the device. The firmware can also determine whether the error count for the device exceeds a threshold. If the error count for the device exceeds the threshold, the firmware can generate an error notification for the device. The firmware can also implement a remedial action policy for the device.

Abstract: Systems and devices can include a first port of a first device coupled to a second port of a second device across a multi-lane link. The first port can augment a data block with error correcting code by distributing error correcting code evenly across each lane of the data block, wherein each lane of the data block includes a same number of error correcting code. The first port can transmit the data block with the per-lane error correcting code to the second port across the multi-lane link. The second port can determine error correcting code based on the error correcting code bits received in the data block, and perform error correction on the symbols of the data block based on the error correcting code received.

Abstract: Methods and apparatus for two-stage ACK/DTX detection. In an embodiment, a method includes determining a first stage DTX value from bit-domain correlation values, and determining a second stage DTX value from symbol domain correlation values generated from candidate ACK bits. The method also includes determining a DTX decision based on the first stage DTX value and the second stage DTX value.

Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.

Abstract: A Built-in-Self-Test (BIST) centric Automatic Test Equipment (ATE) framework can include a host controller and one or more tester units. The host controller can be configured to receive one or more inputs to initiate testing of a plurality of Devices Under Test (DUTs). The one or more tester unit can include a plurality of Universal Asynchronous Receiver-Transmitters (UARTs) communication links. The UART communication links can be configured to send one or more commands for initiating and controlling a Built-in-Self-Test (BIST) in the plurality of DUTs. The UART communication links can also be configured to receive test output data of the BIST from the plurality of DUTs. The host controller can also be configured to output the test output data of the BIST.

Abstract: There are provided a memory controller and a memory system having the same. A memory controller includes: an internal memory for storing error injection information for an error test operation and error test information that is a result of the error test operation; and a central processing unit for receiving first sector data from a host, and performing an error test operation on a memory device according to the error injection information, when the error injection information is included in the first sector data.

Abstract: Embodiments of the invention are directed to a built-in self-test system for an electronic circuit. The system includes a memory having two or more base seeds stored thereon. The system further includes seed generation logic configured to generate, based at least in part on the two or more base seeds, a plurality of generated seeds. The generated seeds can be constructed from the base seeds such that each of the generated seeds encodes a test pattern that satisfies a functional constraint. A finite state machine is configured to generate, based on the plurality of generated seeds, a sequence of constrained pseudorandom test patterns. A test controller is operable to place the electronic circuit into a test mode based on the constrained pseudorandom test pattern.

Abstract: There is provided a communication apparatus, including: a transmission/reception unit that transmits/receives a signal to/from a different apparatus; a confirmation signal detection unit that detects one of a reception confirmation signal and a non-reception confirmation signal, the reception confirmation signal and the non-reception confirmation signal being transmitted from the different apparatus that has received the signal transmitted from the transmission/reception unit; and a conflict avoiding unit that instructs the transmission/reception unit to transmit an abort signal for instructing to interrupt communication after ignoring a predetermined number of bits following the non-reception confirmation signal when the confirmation signal detection unit has detected the non-reception confirmation signal.

Abstract: A method for memory page erasure-correcting property generation in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. Erasure-correcting properties are generated for the data using three nested codes, wherein a first nested code has even parity over planes of class 0, 1 and 2, a second nested code has a first global parity, and a third nested code has a second global parity and a third global parity.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Abstract: The present disclosure relates to processing operations that enable use of cache memory for content validation and error remediation of content. Functionality of the cache is extended to enable interfacing between a cache and a validation component, which is configured to validate data read directly from the cache. Corrupted content may be updated and propagated to a permanent data store associated with an application/service, system, etc. Use of the cache may be optimal for targeting recent and/or heavily accessed content as well as a means for offloading data processing operations from a permanent data storage. Examples described herein extend to those in which data associated with an electronic file is already stored in cache memory as well as those in which update occurs directly to a permanent data storage and subsequently forwarded for validation processing.

Abstract: A memory system can identify target memory units to characterize by generating Cumulative Distribution Function (CDF)-based data for each memory unit and analyzing the CDF-based data to identify target memory units that are exceptional. Such target memory units can be those with CDF-based data with extrinsic tails or that crosses an info limit threshold. The memory system can perform characterization processes for the target memory units, e.g. using an Auto Read Calibration (ARC) analysis or a Continuous Read Level Calibration (cRLC) analysis. A manufacturing process for the memory device can use results of the characterization processes, e.g. by mapping them to types of problems observed during testing. Alternatively, results of the characterization processes to can be used during operation of the memory device, e.g. to adjust the initial read voltage threshold, the read retry voltage values, or the order of read retry voltages used in data recovery.