Abstract: A radio communication apparatus includes a printed board, an RF circuit formed on one surface of the printed board and configured to generate an RF signal, a first transmission line configured to transmit the RF signal, a second transmission line configured to transmit a signal different from the RF signal, and an antenna formed on another surface of the printed board and configured to emit the RF signal. The antenna includes a plurality of dielectric substrates layered on the other surface of the printed board, a metal film formed on surfaces of the plurality of dielectric substrates, and a through hole formed in at least the dielectric substrate adjacent to the printed board. The first transmission line is disposed on the one surface of the printed board, and a part of the second transmission line is disposed between any of the plurality of layered dielectric substrates.

Abstract: Systems and methods for mounting antennas to a vehicle provide for reducing a height by which the antennas extend from a vehicle while maintaining the antennas as the furthest extending component in a vertical direction from the vehicle. The systems and methods also maintain antennas towards an interior of the vehicle, such as inward of a leading edge of the vehicle, in order to reduce risk of damage, displacement, or both of the antennas.

Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.

Abstract: Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

Abstract: Methods and devices for lossy encoding of point clouds. Rate-distortion optimization is used in coding an occupancy pattern for a sub-volume to determine whether to invert any of the bits of the occupancy pattern. The assessment may be a greedy evaluation of whether to invert bits in the coding order. Inverting a bit of the occupancy pattern amounts to adding or removing a point from the point cloud. A distortion metric may measure distance between the point added or removed and its nearest neighbouring point.

Abstract: A method for selectively dropping out feature elements from a tensor is disclosed. The method includes generating a mask that has a plurality of mask elements arranged in a first order. A compressed mask is generated, which includes a plurality of compressed mask elements arranged in a second order that is different from the first order. For example, each mask element of the plurality of mask elements of the mask is compressed to generate a corresponding compressed mask element of the plurality of compressed mask elements of the compressed mask. Individual compressed mask element of the plurality of compressed mask elements is indicative of whether a corresponding feature element of the tensor output by a neural network layer is to be dropped out or retained. Feature elements are selectively dropped from the tensor, based on the compressed mask.

Abstract: Provided is a digital filter that is configured to generate a first integration signal by integrating data groups, which are generated by sampling sample data within a first time period that overlaps with another time period, configured to generate a second integration signal by integrating data groups, which are generated by sampling the sample data within a second time period that is included in the first time period, the first time period and the second time period overlapping with one another, and configured to output a difference between the first and second integration signals as digital data. The first integration signal is generated during a third time period that is included in the first time period.

Abstract: A digital-to-analog converter (DAC) includes a plurality of reference modules, an output capacitor configured to output the analog voltage, and a sharing switch coupled between the output capacitor and the reference modules. The reference modules are mutually connected in parallel. Each reference module includes a reference capacitor and a reference switch connected in series. A plurality of reference capacitances of the reference capacitors are substantially identical. The reference switches are controlled by a plurality of control signals. The control signals are corresponding to a control code. The DAC produces an analog voltage according to the control code. An analog difference, between a first analog voltage corresponding to a first control code and a second analog voltage corresponding to a second control code, monotonically increases or monotonically decreases as a first value corresponding to the first control code increases. The first control code is consecutive to the second control code.

Abstract: A chip antenna includes: a first dielectric layer; a second dielectric layer upwardly spaced apart from the first dielectric layer; a patch antenna pattern disposed on the second dielectric layer; a feed via extending through the first dielectric layer; a feed pattern disposed between the first and second dielectric layers, electrically connected to the feed via, and spaced apart from the patch antenna pattern; and an adhesive layer adhered to the first and second dielectric layers. The adhesive layer includes a cavity surrounding the feed pattern between the first and second dielectric layers and; and a vent disposed between the cavity and an external side surface of the adhesive layer.

Abstract: An information handling system to wirelessly transmit and receive data may include a processor; a memory; an input/output (I/O) device; a wireless adapter; a metal C-cover to house a speaker grill, the speaker grill covering a speaker to emit audio waves; the speaker grill formed within the C-cover to emit a target radio frequency (RF), including: a slot formed around an operative antenna portion of the speaker grill forming a peninsula of the speaker grill in the C-cover; an antenna cavity formed on a back side of the peninsula, the antenna cavity including walls formed around the cavity in the back side of the peninsula; and a tuning module operatively coupled to the speaker grill to excite the speaker grill and dynamically switch frequencies based on the target frequency to be emitted by the speaker grill.

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

Abstract: Methods and systems for implementing and operating antennas, particularly multiple-input and multiple-output (MIMO) antennas, for radio telecommunications.

Abstract: A polarized antenna array is provided that includes multiple polarized antenna elements. The polarized antenna array has a polarization vector defining a co-polarization direction and a cross-polarization direction. The multiple polarized antenna elements include a first sub-set of polarized antenna elements that collectively have a first polarization vector and a second sub-set of polarized antenna elements that collectively have a second polarization vector. Application of a controlled phase difference between the first sub-set of polarized antenna elements and the second sub-set of polarized antenna elements causes constructive combination of the first polarization vector and second polarization vector in the co-polarization direction and destructive combination of the first polarization vector and the second polarization vector in the cross-polarization direction.

Abstract: Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.

Abstract: A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.

Abstract: This application provides a CPE device that includes: a housing, an omnidirectional antenna, a communications module, a PCB, and a heat sink. The omnidirectional antenna is connected to an input end of the communications module, an output end of the communications module is connected to the PCB. An output end of the PCB is connected to an Ethernet cable, and the PCB is disposed on the heat sink. The communications module is configured to convert a received radio-frequency signal to a digital signal. The housing is a cylindrical structure with an opening formed at a lower end. The omnidirectional antenna, the communications module, and the PCB are disposed inside the housing. The heat sink is disposed at the lower end of the housing, and a through hole for the Ethernet cable to pass through is disposed on the heat sink.

Abstract: A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.

Abstract: Examples disclosed herein relate to a switched coupled inductance phase shift mechanism. The phase shift mechanism includes a variable inductor element configured to toggle between a first inductance state and a second inductance state in response to a first control bit value, and a plurality of variable capacitor elements coupled to the variable inductor element and configured to toggle between a first capacitance state and a second capacitance state in response to a second control bit value. The variable inductor element and the variable capacitor elements collectively produce a first phase shift using the first inductance and capacitance states, and collectively produce a second phase shift using the second inductance and capacitance states, where a target phase shift is produced from a difference between the first and second phase shifts. Other examples disclosed herein relate to an antenna array and a method of phase shifting with switched coupled inductance.

Abstract: A method compares text strings having Unicode encoding. The method receives a first string S=s1s2 . . . sn and a second string T=t1t2 . . . tm, where s1, s2, . . . , sn and t1, t2, . . . , tm are Unicode characters. The method computes a first string weight for the first string S according to a weight function ƒ. When S consists of ASCII characters, ƒ(S)=S. when S includes one or more non-replaceable non-ASCII characters, the first string weight ƒ(S) is a concatenation of an ASCII weight prefix ƒA(S) and a Unicode weight suffix ƒU(S). The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights.

Abstract: A housing assembly, an antenna assembly, and an electronic device are provided according to the present disclosure. The housing assembly includes a dielectric substrate and a radio-wave transparent structure. The dielectric substrate has a first transmittance for a radio frequency signal in a preset frequency band. The radio-wave transparent structure includes a first radio-wave transparent layer and a second radio-wave transparent layer coupled with the first radio-wave transparent layer. The first radio-wave transparent layer and the second radio-wave transparent layer are indirectly stacked together, and the radio-wave transparent structure at least partially covers the dielectric substrate. A region of the housing assembly corresponding to the radio-wave transparent structure has a second transmittance for the radio frequency signal in the preset frequency band, and the second transmittance is larger than the first transmittance.