Abstract: A capacitor circuit includes a first capacitor bank and a second capacitor bank. The first capacitor bank includes p switch-capacitor circuits connected to each other in parallel, where p is a natural number of 2 or more, wherein at least two switch-capacitor circuits among the p switch-capacitor circuits have mutually different capacitance values based on a first weight. The second capacitor bank includes q switch-capacitor circuits connected to each other in parallel, where q is a natural number greater than p, wherein at least two of the q switch-capacitor circuits have mutually different capacitance values based on a second weight different from the first weight.

Abstract: A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level.

Abstract: A circuitry for an incremental delta-sigma modulator includes at least an incremental delta-sigma modulator and a sample-and-hold element, the sample-and-hold element being arranged in front of the incremental delta-sigma modulator and providing an input voltage for the incremental delta-sigma modulator in the charged state, wherein the sample-and-hold element includes a capacitor for charging the input voltage for the incremental delta-sigma modulator, wherein a first switch is arranged in front of the capacitor, and a second switch is arranged behind the capacitor, wherein the first switch is open when the second switch is closed so as to provide, at the incremental delta-sigma modulator, an input voltage decreasing in amount, in particular a decaying input voltage, or wherein the second switch is open when the first switch is closed so as to charge the capacitor of the sample-and-hold element. In addition, a method of operating a circuitry for an incremental delta-sigma modulator is proposed.

Abstract: A one-hand mounting system for fixing an antenna module to a vehicle. The mounting system includes a slidable lever, which is configured to perform a translational movement, and a rotatable locking device, which is engaged with the slidable lever to transform the translational movement of the slidable lever to a rotational movement of the rotatable locking device, thereby fixing or releasing the antenna module to or from the vehicle.

Abstract: An autoregressor that compresses input data for a specific purpose. Input data is compressed using a compression/decompression framework and by accounting for a purpose of a prediction model. The compression aspect of the framework is distributed and the decompression aspect of the framework may be centralized. The compression/decompression framework and a machine learning prediction model can be centrally trained. The compressor is distributed to nodes such that the input data can be compressed and transmitted to a central node. The model and the compression/decompression framework are continually trained on new data. This allows for lossy compression and higher compression rates while maintaining low prediction error rates.

Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

Abstract: The present invention provides a receiving circuit, wherein the receiving circuit includes a first ADC, an attenuator, a second ADC, a harmonic generation circuit and an output circuit. In the operations of the receiving circuit, the first ADC performs an analog-to-digital operation on an analog input signal to generate a first digital output signal, the attenuator reduces strength of the analog input signal to generate an attenuated analog input signal, the second ADC performs the analog-to-digital operation on the attenuated analog input signal to generate a second digital input signal, the harmonic generation circuit generates at least one harmonic signal according to the second digital input signal, and the output circuit deletes a harmonic component of the first digital input signal by using the at least one harmonic signal to generate an output signal.

Abstract: An illustrative example embodiment of an antenna device includes a substrate, a plurality of antenna elements supported on the substrate, an integrated circuit supported on one side of the substrate, and a metallic waveguide antenna situated against the substrate. The metallic waveguide antenna includes a heat dissipation portion in a thermally conductive relationship with the integrated circuit. The heat dissipation portion is configured to reduce a temperature of the integrated circuit.

Abstract: A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

Abstract: Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

Abstract: A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.

Abstract: An apparatus of neural network model decompression includes processing circuitry. The processing circuitry can be configured to receive, from a bitstream of a compressed neural network representation, one or more first syntax elements associated with a 3-dimensional coding unit (CU3D) partitioned from a 3-dimensional coding tree unit (CTU3D). The first CTU3D can be partitioned from a tensor in a neural network. The one or more first syntax elements can indicate that the CU3D is partitioned based on a 3D pyramid structure that includes multiple depths. Each depth corresponds to one or more nodes. Each node has a node value. Second syntax elements corresponding to the node values of the nodes in the 3D pyramid structure can be received from the bitstream in a breadth-first scan order for scanning the nodes in the 3D pyramid structure. Model parameters of the tensor can be reconstructed based on the received second syntax elements.

Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.

Abstract: Methods, apparatus, systems, and software for implementing self-checking compression. A byte stream is encoded to generate tokens and selected tokens are encoded with hidden parity information in a compressed byte stream that may be stored for later streaming or streamed to a receiver. As the compressed byte stream is received, it is decompressed, with the hidden parity information being decoded and used to detect for errors in the decompressed data, enabling errors to be detected on-the-fly rather than waiting to perform a checksum over an entire received file. In one embodiment the byte stream is encoded using a Lempel-Ziv 77 (LZ77)-based encoding process to generate a sequence of tokens including literals and references, with all or selected references encoded with hidden parity information in a compressed byte stream having a standard format such as DEFLATE or Zstandard.