Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.

Abstract: An optical communication apparatus includes a level detector, an FIR filter, and a adjustor. The level detector detects level information that discriminates a change in a multi-value level based on an input signal used in a multi-value amplitude modulation system. The FIR filter compensates a signal band of the input signal in accordance with tap coefficients of a plurality of multipliers. The adjustor corrects the tap coefficient of each of the multipliers included in the FIR filter based on the level information detected in the level detector.

Abstract: An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.

Abstract: Described herein is an apparatus having color compression circuitry coupled to a texture unit and shader execution array. The color compression circuitry performs lossless delta color compression of pixel color data provided by the shader execution array and texture unit to generate compressed color data. The compressed color data is stored at one or more levels of a multilevel cache subsystem.

Abstract: Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.

Abstract: A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

Abstract: An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

Abstract: A method for managing data includes obtaining a compression algorithm selection request for a data object, wherein the data object is generated by a production host, identifying, in response to the compression algorithm selection request, a set of production host performance objectives of the production host, performing a compression algorithm selection analysis using the set of production host performance objectives and a compression selection model to obtain a compression algorithm selection for a compression algorithm, specifying the compression algorithm to the production host using a data agent, wherein the data agent is operatively connected to the production host, initiating a compression on the data object using the data agent by applying the compression algorithm to obtain a compressed data object, and initiating a storage of the compressed data object.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: A data processing system and method are provided. The data processing system includes: a data acquisition unit, configured to acquire a plurality pieces of data related to a target object; and a data processing unit, configured to receive the plurality pieces of data and set a plurality of adjacent regions in a two-dimensional spatial representation of the plurality pieces of data according to a tolerable compression error. The plurality of regions include an adjacent first region and second region, respectively covering a plurality pieces of data. The data processing unit is configured to forwardly expand the second region to obtain the expanded second region overlapping the first region, calculate a compression error of data covered by the expanded second region, reset the first region and compress the data covered by the reset first region. The data processing system can reduce or minimize the data compression error.

Abstract: According to one embodiment, a dividing circuit divides a first bit string into second bit strings and outputs the divided second bit strings. The dividing circuit includes first, second, and third blocks. The first block executes first operation for each bit of a third bit string in the first bit string. The first operation is to calculate a head bit of a succeeding symbol when one bit is assumed to be a head of one symbol. The second block executes second operation for each bit of the third bit string for a set number of times. The second operation is to overwrite boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information. The third block divides the third bit string immediately before a second bit indicated by boundary information associated with a first bit of the third bit string.

Abstract: A mobile device includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element and the third radiation element are coupled to a signal source. The second radiation element is coupled to a ground voltage. The second radiation element is adjacent to the first radiation element. The first radiation element, the second radiation element, and the third radiation element substantially extend in the same direction. The fourth radiation element is coupled to the ground voltage. The fourth radiation element is between the first radiation element and the second radiation element. The fifth radiation element is coupled to the ground voltage. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, the fourth radiation element, the fifth radiation element, and the dielectric substrate.

Abstract: A radome structure may include a structural component, an inner tuning layer component underlying the structural component and an outer tuning layer component overlaying the structural component. The structural component may include a first fiber-reinforced dielectric layer that may include a first fiber-reinforced polymer. The inner tuning layer component may include a first inner tuning layer that may include a second fiber-reinforced polymer. The outer tuning layer component may include a first outer tuning layer that may include a third fiber-reinforced polymer.

Abstract: Disclosed are embodiments of a transceiver front-end configured for a reduced noise figure (NF). Each of the embodiments includes an antenna, a transmitter branch and a receiver branch all connected to an input/output pad. The transmitter branch is coupled to the input/output pad (and thereby the antenna) by an impedance transformer. Only the receiver branch is selectively electrically connected to the input/output pad (and thereby the antenna) by a switch. A common matching network between the input/output pad and the switch provides both impedance matching and electrostatic discharge protection for the switch and the low noise amplifier, thereby reducing NF. Specific embodiments are disclosed for integration into specific technologies (e.g., fully depleted silicon-on-insulator (FDSOI) technology and fin-type field effect transistor (finFET) technology).

Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

Abstract: There is provided a computer-implemented method of compressing a baseline dataset, comprising: creating a weight function that calculates a weight for each instance of each unique data elements in the baseline dataset, as a function of sequential locations of each of the instances of each respective unique data element within the baseline dataset, creating an output dataset storing a codeword for each one of the unique data elements, wherein codewords are according to a compression rule defining data elements associated with a relatively higher weight as being associated with codewords that are relatively shorter, dynamically creating the compressed dataset by sequentially iterating, for each current sequential location of the baseline dataset: determining an encoded data element mapped to the respective data element of the current sequential location according to the weight function, and adjusting the codewords of the output dataset according to the current weights to maintain the compression rule.

Abstract: An antenna device configured to be attached to a vehicle includes: an antenna of a resonance type; and a matching circuit connected to the antenna, wherein the matching circuit includes a first matching circuit connected to a feeding portion of the antenna and a second matching circuit connected to a subsequent stage of the first matching circuit, wherein the first matching circuit reduces an impedance in a frequency band that is away to a higher-frequency range or a lower-frequency range from a resonance point of the antenna such that the impedance is lower than before connection of the first matching circuit, and the second matching circuit increases an impedance in a vicinity of the resonance point of the antenna such that the impedance is higher than before connection of the second matching circuit.

Abstract: Methods and systems for encoding and decoding data, such as point cloud data. The methods may include using a coder map to map a range of discrete dependency states to a smaller set of binary coders each having an associated coding probability. The selection of one of the discrete dependency states may be based on a contextual or situational factors, which may include a prediction process, for a particular symbol, such as an occupancy bit. The coder map is updated after each symbol is coded to possibly alter to which binary coder the selected discrete dependency state maps.

Abstract: An antenna includes at least one antenna element mounted on a substrate and extending normally thereto. The at least one antenna element is constructed from a plurality of antenna components, one of which is an upper antenna component that is furthest from the substrate. A support material surrounds the at least one antenna element and is disposed between the antenna components. A material layer is disposed on the upper antenna component and the support material. Heating elements may be interposed between the upper antenna component and the material layer, and an additional material layer, such as an ablative layer, may be disposed on the material layer.

Abstract: There is provided a combined antenna and radome arrangement. The combined antenna and radome arrangement comprises an advanced antenna system (AAS). The AAS comprises antenna elements and is configured for communication in a frequency range of 2.5 GHz to 10 GHz. The combined antenna and radome arrangement further comprises a radome. The radome has a first layer sandwiched between two second layers. The two second layers are of a second dielectric material. The first layer is of a first dielectric material and has a thickness t1, where t1??min/3, wherein ?min is the wavelength of the highest frequency in the frequency range of the AAS. The radome is placed in front of the AAS such that the radome forms a cover for the AAS.