Abstract: There is provided a combined antenna and radome arrangement. The combined antenna and radome arrangement comprises an advanced antenna system (AAS). The AAS comprises antenna elements and is configured for communication in a frequency range of 2.5 GHz to 10 GHz. The combined antenna and radome arrangement further comprises a radome. The radome has a first layer sandwiched between two second layers. The two second layers are of a second dielectric material. The first layer is of a first dielectric material and has a thickness t1, where t1??min/3, wherein ?min is the wavelength of the highest frequency in the frequency range of the AAS. The radome is placed in front of the AAS such that the radome forms a cover for the AAS.

Abstract: A compression engine calculates replacement CRC codes, in predetermined data lengths, for DIF-in cleartext data including cleartext data and multiple CRC codes based on the cleartext data. The compression engine generates headered compressed-text data in which a header including the replacement CRC codes is added to compressed-text data in which the cleartext data is compressed, and generates code-in compressed-text data by calculating multiple CRC codes based on the headered compressed-text data to add the calculated CRC codes to the headered compressed-text data.

Abstract: This application provides examples of a base station antenna, a switch, and a base station device. A connection status between an output port and an input port of a horizontal-dimensional feeding network is changed by using a switch of the horizontal-dimensional feeding network. In different connection statuses, quantities of input ports that are connected to a plurality of output ports of the horizontal-dimensional feeding network are different. The input port of the horizontal-dimensional feeding network is in communication with an antenna port to form a transceiver channel. In this case, a quantity of transceiver channels, of the horizontal-dimensional feeding network, formed in each connection status is different. Therefore, the quantity of transceiver channels supported by the base station device can be changed by using the base station antenna without a need of replacing the base station antenna.

Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

Abstract: An antenna element comprises a housing having a base and a conducting plate, and a feeding element. The housing has a cavity formed between the base and the conducting plate. The conducting plate has a radiating slot with a length and a width that extends longitudinally along a first axis and a second axis, respectively. The radiating slot has a first and a second edge along the first axis. The feeding element has a feeding point, a feeding line, and a stub. The feeding line extends along the second axis of the conducting plate across the width of the radiating slot such that a first end of the feeding line is coupled with the feeding point on one side of the radiating slot, and a second end of the feeding line extends past the second edge, and the stub extends laterally of the feeding line.

Abstract: The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample.

Abstract: A stream decompression circuit is disclosed. The stream decompression circuit includes a coding length first-in-first-out (FIFO) and a calculation circuit. The coding length FIFO is coupled to a variable length coding (VLC) circuit and used to store a coding length that the VLC circuit codes sub-streams and output a specific number of bits when the coding length accumulates over the specific number of bits. The calculation circuit is coupled between the coding length FIFO and a multiplexer circuit and used to calculate a number of bits required for decompression and output an output multiplex control signal to the multiplexer circuit to control the multiplexer circuit to output the sub-streams according to a specific order.

Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Abstract: A pulse width modulation (PWM) digital-to-analog conversion circuit includes switches 102, 104, 114, 116 controlled by a first PWM signal, and switches 106, 108, 110, 112 controlled by a second PWM signal. A first operational amplifier (op-amp) includes a first input coupled to an output of a filter, and a second input coupled to an output of the first op-amp. During a first time period, an output of a second op-amp is coupled to an input of the filter via switches 102 and 104, and an output of a third op-amp is coupled to the output of the first op-amp via switches 114 and 116. During a second time period, the output of the second op-amp is coupled to the output of the first op-amp via switches 106 and 108, and an output of the third op-amp is coupled to the input of the filter via switches 110 and 112.

Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.

Abstract: A vehicular antenna device includes an antenna portion having an antenna element, and a frame accommodating a heat generation member. The vehicular antenna device is configured to be attached to an attachment portion of a vehicle. The frame includes a first space portion having a cylindrical shape and defining a first space, the first space portion being exposed to an outside air in a condition where the vehicular antenna device is attached to the vehicle. The heat generation member is located along a second surface of the frame that is a reverse side of a first surface defining the first space. The antenna portion is detachable from the frame.

Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

Abstract: An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

Abstract: The preset invention relates to a dual polarized antenna and an antenna array and, more particularly, to a dual polarized antenna comprising: a top portion having a radiation patch; a bottom portion forming a probe; and side portions formed along the outer peripheral edge of the top portion so as to have a predetermined height, wherein the side portions include a cup-shaped aluminum structure, and the top portion, the bottom portion, and the side portions are formed in an integrated form.

Abstract: A multiband antenna has a plurality of first, unit cells and second unit cells. Each first unit cell has two high band radiator clusters and two low band radiators disposed approximately in the center of each of the high band radiator clusters. Each second unit cell has two high band radiator clusters and one low band radiator that is disposed between the two high band radiator clusters. The first unit cell is designed for a superior low band gain pattern, and the second unit cell is designed for a superior high band gain pattern. By selectively arranging the first and second unit cells in a specific heterogeneous pattern, the characteristics of the two unit cells may advantageously and constructively combine to form a high performance antenna gain pattern that is consistent across the low band and high band.

Abstract: A single polarized radiator comprising a plurality of planar notch radiating elements arranged on a dielectric substrate. Each notch radiating element comprises: a metallized region on a first side of the dielectric substrate extending across the width of the notch radiating element from a forward edge of the notch radiating element to a rear edge of the notch radiating element, a tuning element in the metallized region adjacent to a feeding point of the notch radiating element, a notch extending from the tuning element to the forward edge of the notch radiating element thereby creating a notch profile, and a plurality of indentations in the metallized region along each side of the notch to extend the length of the notch profile.

Abstract: The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits also depends upon the value of the first sample.

Abstract: In patent application Ser. No. 15,934563, a method was developed that achieves wave rotation or shaping in the near field and far field, for narrowband RF Signals. That is, using an acoustic or RF phased array, the effective wavefront can be rotated from the propagation normal, at a selected location region in space. In this innovation, the application has been extended to Wideband Signals, where the signal bandwidths can highly exceed the one-percent of carrier frequency narrowband threshold.

Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form.

Abstract: A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.