Abstract: An apparatus includes a processor and a machine-readable medium having program code to cause the apparatus to obtain a first dictionary based on a first training set of signals and determine a first subset of the first training set of signals based on a training reconstruction accuracy threshold and the first dictionary, wherein each atom in the first dictionary includes at least one of a signal pattern and a function representing the signal pattern. The program code also includes code to generate a second dictionary based on a second training set of signals, wherein the second training set of signals includes the first subset of the first training set of signals.

Abstract: A method for transmitting information using a pulse may comprise transmitting, via a channel between a first device and a second device, an idle state for an idle time; and transmitting, via the channel, a pulse state for a pulse time, wherein the idle time and the pulse time define a value for a data word being transmitted, and wherein the duration of one or more of the idle time and the pulse time vary depending upon the value of the data word.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a storage storing a matrix included in an artificial intelligence model, and a processor. The processor divides data included in at least a portion of the matrix by one of rows and columns of the matrix to form groups, clusters the groups into clusters based on data included in each of the groups, and quantizes data divided by the other one of rows and columns of the matrix among data included in each of the clusters.

Abstract: A resolver signal processing apparatus processes a resolver signal output from a resolver by applying an excitation signal generated by an excitation signal generating unit. In particular, the resolver signal processing apparatus includes: a resolver signal processing unit, in which the resolver signal processing unit includes a resolver signal acquiring unit receiving the resolver signal and extracting pole information of the resolver signal, a resolver phase compensating unit compensating a pole acquisition time of extracting the pole information of the resolver signal acquiring unit, and a resolver-digital converter outputting a digital signal by using the pole information extracted from the resolver signal acquiring unit, and a resolver signal processing method using the same.

Abstract: The disclosure provides a look-up table (LUT) compression method and a LUT reading method for computation equipment and its host and device. In a LUT compression phase, the host retrieves an original data from an original LUT by using an original table address, checks the original data according to a reconstruction condition to obtain a check result (bitmap), converts the original data into a reconstructed data according to the check result, writes the reconstructed data to a compressed LUT by using a compressed table address, writes a relationship among the original table address, the compressed table address, and the check result (bitmap) to a mapping table, and stores the compressed LUT to the device.

Abstract: In an embodiment a method for operating a gas sensor arrangement includes generating a sensor current by a gas sensor, converting the sensor current into a digital comparator output signal in a charge balancing operation depending on a first clock signal, determining from the digital comparator output signal an asynchronous count comprising an integer number of counts depending on the first clock signal, determining from the digital comparator output signal a fractional time count depending on a second clock signal and calculating from the asynchronous count and from the fractional time count a digital output signal which is indicative of the sensor current generated by the gas sensor.

Abstract: A metastable state detection device and method, and an ADC circuit are disclosed. The metastable state detection device includes: a delay unit which is configured to receive a synchronization signal and delay the synchronization signal based on preset step delay values; a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal; the first data input terminal is configured to receive the delayed synchronization signal; a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal; a processing module connected to the second data output terminal, which is configured to receive a target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal.

Abstract: A time interleaved analog-to-digital converter (TIADC) is provided. The TIADC converts an input signal into a digital output signal and includes N analog-to-digital converters (ADCs), a clock generation circuit, and a control circuit. The N ADCs receive the input signal and sample the input signal according to N sampling clocks to each generate a digital output code, N being an integer greater than or equal to 2. The clock generation circuit is configured to receive a working clock and a set of control values and to generate the N sampling clocks according to the set of control values and the working clock. The control circuit is configured to periodically generate the set of control values based on a pseudo random number and to output the digital output codes in turn as the digital output signal.

Abstract: A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

Abstract: Disclosed are a system and a battery management integration circuit using an incremental analog-to-digital converter (ADC), which can reduce the consumption of the amount of a bias current. The system includes an incremental ADC configured to perform accumulation on an analog signal during an oversampling period and a bias current generator configured to provide a bias current for the accumulation of the incremental ADC. The bias current generator provides a first amount of the bias current in a first period defined from start timing of oversampling to preset timing during the oversampling period, and provides a second amount of the bias current, smaller than the first amount of the bias current, in a second period subsequent to the first period.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT). The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.

Abstract: A device is provided comprising a first oscillator based analog-to-digital converter configured to receive an analog input signal and output a first digital signal and a second oscillator based analog-to-digital converter configured to receive an analog reference signal and output a second digital signal. The device further comprises output logic configured to generate a digital output signal based on the first digital signal and the second digital signal.

Abstract: A mobile communication antenna comprises a radome, a reflector arrangement, mobile communication radiators, and at least one electronic module. The radiators are arranged on a front side and the at least one electronic module is arranged on a rear side of the reflector arrangement. At least one electronic module comprises an electronic unit and a module housing within which the electronic unit is arranged. The module housing is made of metal and comprises a front side, a rear side, end faces and side walls, wherein the front side of the module housing points in the direction of the radome and the rear side of the module housing points in the direction of the rear side of the reflector arrangement. At least the surface of the front side and/or the rear side of the module housing is at least predominantly coated with a heat emission layer.

Abstract: Apparatus and methods for reconfigurable antenna systems are provided herein. In certain configurations, an antenna system includes an antenna element, a tuning conductor adjacent to and spaced apart from the antenna element, and a switch electrically connected between the tuning conductor and a reference voltage, such as ground. The tuning conductor is operable to load the antenna element, and the switch selectively connects the tuning conductor to the reference voltage to provide tuning to the antenna element.

Abstract: A system and method for highly efficient encoding of data that includes extended functionality for asymmetric encoding/decoding and network policy enforcement. In the case of asymmetric encoding/decoding the original data is encoded by an encoder according to a codebook and sent to a decoder, but the output of the decoder depends on data manipulation rules applied at the decoding stage to transform the decoded data, into a different data set from the original data. In the case of network pokey enforcement, a behavior appendix into the codebook, such that the encoder and/or decoder at each node of the network comply with network behavioral rules, limits, and policies during encoding and decoding.

Abstract: An electronic device includes a decoding subsystem having a symbol decoder and a second symbol resolver with a plurality of local symbol decoders and a symbol selector. The symbol decoder outputs a first symbol decoded from an initial code for which a symbol is available in a block of the compressed data. The second symbol resolver decodes, in each local symbol decoder, substantially in parallel with decoding the first symbol in the symbol decoder, a respective symbol from a subsequent initial code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver outputs, by the symbol selector, as a second symbol, one of the respective symbols from the local symbol decoders selected by the symbol selector based on the initial code.

Abstract: A sigma-delta modulation device includes a detection circuit and a sigma-delta modulator. The detection circuit is configured to detect an input signal to generate a detection signal, and compare the detection signal and a threshold to generate a control signal. The sigma-delta modulator is coupled to the detection circuit and configured to store a plurality of noise transfer functions, select one of the noise transfer functions according to the control signal, and convert the input signal into an output signal according to the noise transfer function.

Abstract: Circuits, methods, and apparatus for efficiently implementing encoding and decoding between binary and multilevel data.

Abstract: A data compression method includes obtaining N to-be-compressed data blocks and N pieces of protection information (PI), where the N to-be-compressed data blocks are in a one-to-one correspondence with the N pieces of PI, and N is a positive integer greater than or equal to 2, compressing the N to-be-compressed data blocks to obtain a compressed data block, and compressing the N pieces of PI to obtain compressed PI.