Abstract: A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

Abstract: The present invention provides a computer-implemented method, computer system and computer program product for data compression. According to the computer-implemented method, one or more data blocks on a data source to be replicated to a data target may be detected. Then, compression performance of a first compression dictionary may be evaluated. The first compression dictionary may be previously used to compress existing data on the data target. If the compression performance is lower than a preset performance threshold, a second compression dictionary may be generated based on the existing data on the data target. The data target may be updated based on the existing data and the one or more data blocks using the second compression dictionary.

Abstract: A system collects statistical data for a data page, divides the data page into parts, analyzes the data page and the statistical data, based on compression efficiency of one or more compression methods for each part of each page, to determine a compression method for each part of page, and compresses, based on the analyzing, the parts of the data page.

Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Abstract: An antenna device provided with a single reflecting mirror having multiple focal points, and multiple primary radiators provided at respective positions of the multiple focal points.

Abstract: Embodiments of the present disclosure integrate magnetoelectric nanowire arrays within antenna assemblies to form ultra-compact antennas. An exemplary nanowire antenna array device comprises a first electrode positioned across a second electrode, wherein an electrode gap separates the first electrode and the second electrode; and a magnetoelectric nanowire connected to the first electrode and the second electrode across the electrode gap without substrate clamping, wherein the nanowire antenna array device receives or transmits electromagnetic waves through the magnetoelectric effect.

Abstract: Examples disclosed herein relate to a switched coupled inductance phase shift mechanism for beamsteering an antenna array and applied in a radar system or a communication system. The phase shift mechanism includes a variable inductor element configured to toggle between a first inductance state and a second inductance state in response to a first control bit value, and a plurality of variable capacitor elements coupled to the variable inductor element and configured to toggle between a first capacitance state and a second capacitance state in response to a second control bit value. The variable inductor element and the variable capacitor elements collectively produce a first phase shift using the first inductance and capacitance states, and collectively produce a second phase shift using the second inductance and capacitance states, where a target phase shift is produced from a difference between the first and second phase shifts.

Abstract: Various embodiments include methods and devices for compression and decompression of weight data sets. Some embodiments may include compressing weight data by receiving a weight data set of binary numbers representing weight values, generating a frame payload including a compressed first frame of a first subset of the weight values in the weight data set, and generating a block of compressed weight data having the frame payload. Some embodiments may include decompressing weight data by retrieving a block of compressed weight data, in which the block of compressed weight data includes a frame header associated with a frame payload, in which the frame header includes a normalization factor indicator, and in which the frame payload includes compressed weight values, and generating a first decompressed frame comprising decompressed weight values of the compressed weight values of the frame payload.

Abstract: Embodiments include performing decompression of a file. Aspects include receiving a compressed input stream for the file and processing the compressed input stream, by two or more pipelines in parallel, to create an output vector, wherein each pipeline includes a first decoder and a second decoder. Aspects also include writing, by each of the two or more pipelines, entries onto a scratchpad in an order defined by the output vector and writing one or more entries from the scratchpad to a main history buffer based on a determination that a validity field of the one or more entries has a value of true.

Abstract: A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.

Abstract: An encoding method includes traversing a to-be-encoded string, searching for a preset string in the to-be-encoded string, and deleting the preset string in the to-be-encoded string if the preset string is found, to obtain a target string.

Abstract: Example embodiments relate to systems and methods for analog-to-digital signal conversion. One embodiment includes a system for analog-to-digital signal conversion. The system includes an analog input signal. The system also includes a digital-to-analog converter configured to generate a reference signal. Further, the system includes an amplifier configured to amplify an error signal that includes a difference between the analog input signal and the reference signal. Additionally, the system includes a level-crossing based sampling circuit that includes a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level, thereby generating event-based reset signals corresponding to a plurality of sampling instances in order to reset the digital-to-analog converter.

Abstract: Examples of the disclosure describe systems and methods for implementing a file compression system. In an example method, a source string to be compressed is received. The source string comprises a plurality of characters. A first frequency is determined for each character of the plurality of characters of the source string. A first tree corresponding to the source string is determined based on the first frequencies. The source string is encoded using the first tree to generate a first encoded string. It is determined whether a total number of bits in the first encoded string is a multiple of eight. In accordance with a determination that the total number of bits in the first encoded string is not a multiple of eight, the first encoded string is appended with zeroes so that a new total number of bits in the first encoded string is a multiple of eight.

Abstract: In aspects of a small cell installation structure, a support structure provides stability and an attachable framework to mount wireless technology equipment. A formable aesthetic housing is formed around the support structure, and a hardened polymer coating over the formable aesthetic housing is adapted to a shape of the formable aesthetic housing and the support structure. The hardened polymer coating resists environmental conditions that may otherwise interfere with performance of the wireless technology equipment. Additionally, an antenna housing module encloses antennas of the wireless technology equipment, is integrated with the support structure, and is designed to pass millimeter wave (mmW) spectrum wireless signals.

Abstract: Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.

Abstract: A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.

Abstract: A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between a unipolar or bipolar analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.

Abstract: A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.

Abstract: An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

Abstract: An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.