Abstract: A semiconductor circuit assembly having capacitively controlled field effect transistors, includes a semiconductor chip containing a digital circuit part for supplying timing pulses for controlling operation of the digital circuit part, and terminal having at least one conductive connection to the digital circuit part and the timing pulse generator for supplying potentials thereto from a direct current source. An oscillator is provided and a substrate-bias generator connected to the oscillator and the timing pulse generator. The substrate-bias generator is controlled by the oscillator for producing a bias voltage able to reach a given full value and for activating the timing pulse generator only after the substrate bias voltage has reached its full value.

Abstract: The present invention provides a circuit for second correlated sampling. By switchably connecting feedback in the circuit, the stage providing the second correlated sampling is precharged independent of an external reference voltage source to make the circuit simpler and hence integratable.

Abstract: Apparatus and method for performing a logical not function in a multi-compare environment is disclosed. By performing two equivalence compares of a measured variable against selectable target values and using the result of the equivalence compares to selectivity set or reset a bistable element, the need for inverting and multiplexing the output of a comparator that is otherwise required when performing a NOT equivalence function in a single-compare environment is eliminated. The not function logic is used in a system analyzer connected to a data processing system and is used to selectively enable the tracing of software execution as a function of whether or not a variable is a predefined value.

Abstract: Four-pole circuits for iterative modular use in integrated circuits fabricated with complementary MOS (C-MOS) technology or LOCMOS technology, having a high density of circuit elements and high speed obtained at low dissipation. Each of said four-pole circuit modules has two signal inputs, a control input and a signal output line. The four-pole circuit modules may be constructed from two series connected complementary MOS transistors or two series-connected p-MOS transistors. In the latter case the control input must be doubled to receive the control signal and its inverted value. The signal outut is then alternatively connected to one of the two signal inputs (logically or physically) by each of the two values of the control signal.

Abstract: An input buffer to which an ECL logic swing is applied through a voltage level shifter to one input of a differential pair of switching devices, the other input of the differential pair being a voltage level shifted by the same amount from an ECL logic reference voltage. The output across a load device coupling one of the switching devices to a collector voltage source drives the input of a conventional inverter coupling a reduced MOS logic voltage supply to the collector voltage source. An output buffer to which a reduced MOS voltage swing logic input is applied to the input of a conventional inverter coupling a reduced MOS logic voltage supply to a collector voltage source. The output of the inverter is applied to one input of a differential pair of switching devices having the other input thereto held at a reference level defined by a voltage divider.

Abstract: A field-effect capacitance includes a first region of a first conductivity type in a semiconductor layer, which region is provided with at least one contact electrode connected to a first terminal and with an insulated electrode arranged on said region and connected to a second terminal. A second semiconductor region of a second conductivity type opposite to the first conductivity type is formed in the semiconductor layer, which second region is provided with at least one contact electrode coupled to the first terminal, and with an insulated electrode arranged on said second region and connected to the second terminal. The two capacitances thus formed are then alternately operative for alternate polarities of the signal voltage. The resulting capacitance structure is suitable for high signal voltage applications, and provides a smooth transition when alternate signal polarities are applied.

Abstract: An MOS switching circuit for switching a higher voltage (e.g., 20 volts) with a lower voltage control signal, (e.g., 5 volts). The switching circuit, unlike prior art circuits, does not draw power from the higher voltage supply. The circuit is ideal for integrated circuits where the higher voltage is generated on-chip.

Abstract: The invention discloses a monolithic integrated reference voltage source consisting of a source-drain series arrangement of a depletion-type n-channel MOSFET connected to the supply potential and of an enhancement-type n-channel MOSFET connected to a reference potential. The gate electrode of the depletion-type transistor is connected to the reference potential, while the reference voltage is taken off the point connecting the two transistors, to which point the gate electrode of the enhancement-type transistor is connected. When certain manufacturing requirements are observed as regards the gate oxide layer thickness, the substrate doping and the ratio r of the width-to-length ratio (W=width and L=length of the conducting channel), the circuit displays a very small temperature dependence of the reference voltage and a small surface requirement.

Abstract: A current mirror biasing arrangement for an electronic circuit, particularly one intended for an integrated circuit employs a current mirror constituted by series connected pnp and npn transistors having their collectors connected together. A pair of series-connected field effect transistors (FET) connected between a voltage source and ground have their gates connected to the emitter and collector of the pnp transistor and their junction to the pnp transistor base. The pnp transistors to be biased have their bases connected to the said FET junction. The gate current of the operative FET can be made negligible so that substantially perfect matching is obtained between the npn transistor current and the "mirror" biasing current. Preferably the FET are of subsurface junction type, their low pinch-off voltage and low gate current making them particularly suitable for low voltage application.

Abstract: An ac coupled, chopper stabilized differential comparator circuit characterized receiving a differential signal voltage applied between a signal input terminal and a reference signal input terminal, providing differential outputs at a first and second differential output terminal and being characterized as operating from a voltage source with respect to a reference potential comprising: amplifier means, characterized by a first stage differential amplifier having, a first channel amplifier having an input terminal and an output terminal. The first channel amplifier output terminal is connected to the first differential output terminal. The first stage differential amplifier also has a second channel amplifier having an input terminal and an output terminal. The second channel amplifier output terminal is connected to the second differential output terminal. The gain of the second channel amplifier is essentially equal to the gain of the first channel amplifier.

Abstract: A bias current reference circuit is disclosed having a first diode-connected bipolar device connected in series with an MOS device to develop a reference voltage which is proportional to a bias current. The reference voltage is used by an MOS device connected in series with a resistor which is connected in series with a second diode-connected bipolar device to develop a reference current which is proportional to the difference in the base to emitter voltages of the two bipolar devices. The reference current is used by a diode-connected MOS device to develop a bias voltage which is proportional to the reference current. The bias voltage in turn is used by another MOS device to develop the bias current in proportion to the bias voltage. The bias voltage is also used by other MOS devices to provide similar bias currents. In the disclosed embodiment, such a bias current can be used by a diode-connected CMOS device to develop a complementary bias voltage.

Abstract: GaAs digital electronics uses mainly depletion mode MESFET technology. In typical circuits, negative voltage logic input signals are required while the output voltage is positive. To connect gates, level shifters are needed to shift the positive voltage output signals such that they become suitable for the input to the next gate. A capacitor is used which performs the level shifting. As the charge leaks off the capacitor, the voltage level has to be readjusted periodically, leading to a "dynamic" circuit. A method for self-biasing of the capacitor for readjustment of the voltage level is taught.

Abstract: In a buffer circuit comprising a first, a second and a third transistor and a capacitor for bootstrap action, an inverter is connected to the output point at which the second and third transistors are connected in series, the inverter inverting the potential of the output point and supplying the inverted potential to the gate of the first transistor, thereby ensuring the quick rise of the leading edge of the output signal.

Abstract: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

Abstract: A three state output circuit which pulls down the output node thereof to a first supply voltage in response to an assert signal, pulls up the output node to a second supply voltage in response to a rescind signal, and then presents a high impedance on the output node immediately after the output node is pulled up to a selected reference voltage.

Abstract: A bias circuit for an FET switch in which a pinch-off voltage is generated and sets up a current through a first resistor. The current is reflected through a second resistor to establish a voltage differential across the second resistor which is then imposed across the gate-source terminals of the switch FET when it is desired to turn the switch OFF. The relationship of the turn-off voltage imposed across the switch FET to its pinch-off voltage is determined by the ratio of the resistance values of the two matched resistors, which ratio is independent process and temperature. The switch bias circuit thus offers highly reliable operation and at the same time a greatly reduced power consumption.

Abstract: A simple six-transistor input buffer for generating and applying binary function test signals to associated circuitry in an integrated circuit package. The buffer recognizes three different voltage levels of an input signal that is applied to a single input test pin and generates three corresponding binary output signals that may be used for testing various functions of the associated circuitry.

Abstract: A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

Abstract: A reference voltage generating circuit comprising a depletion mode FET transistor connected to provide a constant current source coupled between a supply voltage and an output node. Three serially connected enhancement mode FET transistors are connected between the output node and a reference voltage. The first enhancement mode device is diode coupled to provide an enhancement threshold voltage offset, the second enhancement mode device has its gate electrode connected to the supply voltage to compensate for variations in supply voltage and the third enhancement device has its gate electrode connected to a source follower circuit. The source follower circuit comprises two serially connected depletion mode devices which receive an input from the output node and provide a feedback output to the gate electrode of the third enhancement mode device so that a constant voltage of a predetermined magnitude is maintained at the output node.

Abstract: A dynamic shift register circuit comprises an input terminal and an output terminal. It further comprises a first transfer gate circuit connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal; an inverter circuit for inverting a level of an output signal of the first transfer gate circuit; a second transfer gate circuit connected to the inverter circuit for receiving an output signal of the inverter circuit and transferring the same under the control of a second clock signal which has a level opposite to that of the first clock signal; a signal follower circuit for producing an output signal having a level which follows a level of the output signal of the first transfer gate circuit; and a logic circuit connected to first and second power source voltages.