Abstract: A drive circuit which can drive an IGFET in a non-saturated region over a long period time without reduction in level is disclosed. The drive circuit comprises a series circuit of a plurality of directional elements connected between a power supply terminal and an output terminal, a plurality of control terminals receiving repetitional signals and a plurality of capacitors coupled between the control terminals and intermediate junctions of the series circuit.

Abstract: Gating circuitry is provided for controlling a plurality of power FETs stacked in series and parallel. A plurality of parallel circuit branches are connected between main terminals, each branch having a plurality of series connected power FETs. All power FETs are turned ON and OFF from a single gate terminal. Trigger means responds to one polarity gate signal to supply gate charging current to all the FETs. The trigger means responds to the opposite polarity gate signal to directly deplete gate charge from selected power FETs. The remaining power FETs have their gate charges depleted through individual self turn-off circuits between their gate and source which becomes conductive in the absence of gate charging current.

Abstract: A bidirectional power FET circuit for AC application has a plurality of pairs of enhancement mode power FETs. Each pair has first and second power FETs connected drain to drain in series relation. The pairs are stacked in series between first and second main terminals. A plurality of gating circuits, one gating circuit for each power FET pair, are stacked in series for driving the power FET pairs sequentially into conduction from a single gate terminal.

Abstract: Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.

Abstract: Stacked gating circuitry is provided for controlling a plurality of pairs of power FETs stacked in series, each pair being bidirectionally source to source connected for AC conduction. All the power FETs turn on from a single gate terminal through series connected current sources, one current source for each FET pair. The FETs turn on in ripple effect.

Abstract: A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that has an enhanced transition from the active high to the active low. An output means includes a first transistor for supplying current to the output and a second transistor for sinking current from the output. A phase splitter means coupled to the output means determines the conductivity of the first and second transistors. An input means is responsive to an input signal and controls the phase splitter means. An output enable means is provided that disables both the first and second transistors for providing the high impedance output. A feedback means for enhancing the downward transition of the output signal from an active high to an active low includes a feedback transistor having a base connected to a supply voltage terminal by a resistor which can be used to vary the speed of the downward transition.

Abstract: A flip-flop circuit of set-reset type comprising complementary MOS transistors.The flip-flop circuit comprises a first CMOS NOR circuit to which set signal is applied, and a second CMOS NOR circuit having same arrangement as the first CMOS NOR circuit and to which reset signal is applied.Set signal is the logical product signal of first set signal and second set signal. Reset signal is the logical product signal of first reset signal and second reset signal. Neither of first set and reset signals becomes logic "1" simultaneously. Second set and reset signals are kept either unchanged during the time period when first set and reset signals are logic "1" or become logic "1" only during the time period when first set and reset signals are logic "1".

Abstract: A high-speed logic inverter, in the form of an integrated circuit, with a single supply source, using field-effect transistors of the "quasi-normally-off" type, and the logic operators having several inputs and several outputs which derive therefrom.One embodiment of the invention starts from an inverter with input, through a diode, on a field-effect transistor gate, and with its output at the source of a field-effect transistor. This basic diagram is added to by providing the input (between supply pole and input terminal) with two pairs of diodes ending at the gates of a dual-gate transistor, and by providing independent outputs obtained by connecting the common drain connected transistor gates to the supply pole distinct from ground.

Abstract: An interface circuit for an integrated injection logic circuit comprises a current mirror circuit having its input current value set by a first resistor and its input controlled by an output signal of the integrated injection logic circuit, a second resistor connected to a current path at the output side of the current mirror circuit, and output means connected to the current output terminal of the current mirror circuit.

Abstract: A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

Abstract: Two flip-flop circuits are employed to provide a positive output and an its inversion output so as to produce the inverted signal of an input signal necessary to provide the function of an exclusive-OR circuit.

Abstract: A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node.

Abstract: An R/S latch circuit employing four IGFETs, one pair of P-channel IGFETs, and another pair of N-channel IGFETs. The P-channel IGFETs have channels respectively connecting Q and Q data output nodes to +V.sub.DD, and gates cross-connected to the opposite data output nodes. The N-channel IGFETs have channels respectively connecting the Q and Q data output nodes to ground, and have gates which respectively comprise the Reset (R) and Set (S) data inputs. A pair of high impedance leakage current paths may also be provided respectively electrically connecting the Q and Q data output nodes to ground. Particular integrated circuit R/S latch structures are disclosed.

Abstract: An MOS driver circuit having a capacitive voltage booster is provided. A first capacitor which is charged to a supply voltage potential is used to control a precharge device which charges a second capacitor. The charge on the second capacitor is sequentially translated by a logic portion to provide a boosted driver voltage which is substantially greater than the supply voltage to an active driver circuit. The output driver circuit may be completely disabled to eliminate a standby current in the output.

Abstract: A tracking ROM drive and sense circuit for use on a monolithic integrated circuit for driving a ROM, the ROM having a ROM input terminal and a ROM output terminal. The invention circuit comprises a sense amplifier having an input terminal coupled to the ROM output terminal and a drive circuit having an output terminal coupled to the ROM input terminal. The sense amplifier provides an output signal at a sense amplifier output terminal in response to a ROM output signal voltage at the sense amplifier input terminal as the ROM output signal penetrates a predetermined sense amplifier threshold voltage. The drive circuit has an amplifier that is essentially identical to the sense amplifier. The drive circuit provides a drive voltage to bias the midpoint of the ROM output signal voltage to track the threshold of the sense amplifier threshold in a sense amplifier threshold voltage, temperature dependent, voltage source dependent and process dependent, change accommodating relation.

Abstract: A chip selection circuit connected to select one of a plurality of semiconductor circuits including at least one memory circuit for addressing purposes, comprises first and second circuit elements directly coupled to each other at a point, at least one of the first and second circuit elements comprising an MOS transistor where the gate electrode is connected to the source electrode, a power source being applied between the first and second circuit elements by the application of a first voltage to the first circuit element and a second voltage to the second circuit element, and an exclusive AND gate circuit provided for receiving the output from the point and chip selection enabling signals to provide chip selection signals.

Abstract: In a semiconductor device having a signal line on which a voltage higher than the voltage supply is generated, a conductive layer following the potential variance of the voltage supply is positioned under an insulating film directly below the signal line in order to make the level of the signal line follow the potential variance of the voltage supply.

Abstract: A structure and method are provided wherein a single output buffer stage (50) is provided which can be programmed to function either as an open drain output buffer or a CMOS Push-Pull output buffer. The output buffer stage constructed in accordance with this invention is programmed in one of several manners. In one embodiment of this invention, the fabrication steps utilized to program the output buffer are the enhancement and depletion dopings, whereby certain devices of the output buffer are programmed to either remain always turned off or always turned on, thus programming the output buffer to serve either as an open drain output buffer or as a CMOS push-pull output buffer.

Abstract: An output buffer circuit for use in a bidirectional input/output circuit comprising an inverter circuit including a pull-up load and a driver transistor, and a charging circuit for charging an external input/output line for a predetermined time-period when the falling of the potential of an internal output line is detected.

Abstract: A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.