Abstract: A memory circuit comprises a plurality of memory cells and a plurality of sense circuits each including first and second input MOS transistors and first and second load MOS transistors of a first channel type and a load circuit connected to the sense circuit and including first to fourth load MOS transistors of a second channel type. The first and second input MOS transistors have their sources connected to each other and their gates connected to receive a differential input signal therebetween from said memory circuits of the first and second switching transistors which have their sources connected respectively to the drains of said first and second input transistors and their gates connected to a column selection signal. The first and second load MOS transistors have their drains connected in common to the drain of the first switching MOS transistors and their sources connected to each other.

Abstract: This describes a tristate driver circuit designed such that it will not be destroyed by excessive high voltage conditions when two such drivers are connected to a bus at the same time. The circuit accomplishes this with parallel high current, low impedance and low current, high impedance output devices, coupled to means for causing the high current, low impedance devices to supply, to the circuit output, only the initial high currents required without inhibiting the low current, high impedance devices from maintaining the steady state conditions needed to clamp the output at the desired output level. The circuit is arranged to cause both high and low current output devices to be initially conductive to charge the output terminal to the desired level, but to subsequently shut off the high current, low impedance device while keeping the low current, high impedance device in a condition to clamp the output at the desired level.

Abstract: An emitter-coupled logic circuit device comprises first and second voltage supply lines connected, respectively, to ground and an external voltage source, a third voltage supply line, having a potential between that of the first and second voltage supply lines, an output buffer circuit connected between the first and third voltage supply lines, and an inner gate circuit connected between the third and second voltage supply lines. The current flowing through the output buffer circuit also flows through said inner gate circuit.

Abstract: A TTL to high level translator having improved high state current drive includes a push-pull output stage and a lateral PNP transistor for supplying current drive when the translator is in a high state. The output stage consists of a pair of Darlington connected transistors comprising an upper amplifier and a lower transistor amplifier connected in series with the upper amplifier. A current transient suppressor circuit circuit is coupled with the bases of the pair of Darlington connected transistors for inhibiting power supply current spikes as the upper and lower amplifiers are alternately turned on and off in response to the TTL logic signal switching between upper and lower level states.

Abstract: A circuit for carrying data between a host system and a remote unit includes first and second edge-triggered delay-type flip-flops coupled to first and second input lines, respectively. Combinational logic coupled to the output of the first flip-flop and to the first and second input lines transmits data on at least one of the input lines to the remote unit. This creates a redundancy which provides for the continued transmission of data between the host and the remote unit in the event that one of the input channels fails.

Abstract: A CMOS level shifter with a reference voltage generator provides a TTL to CMOS input buffer. The reference voltage generator provides a reference voltage which is responsive to the voltage level of the TTL input signal. The reference voltage is kept sufficiently low to prevent an input P channel transistor from turning on when the TTL input signal is at a logic high even when the voltage level is at a minimum for a logic high.

Abstract: An integrated circuit and method includes a substrate bias voltage control circuit formed on a common substrate therewith for ensuring that the substrate has a voltage applied thereto while a semiconductor device on the substrate has a supply voltage applied thereto which includes means for providing sources of bias and supply voltages to the substrate with means for firstly coupling the bias voltage to the substrate when the bias voltage is present and means for secondly coupling the supply voltage to the substrate when the bias voltage is not present.

Abstract: A dynamic signal generation circuit comprising a semiconductor circuit for receiving two input clock signals .phi. and .phi. out of phase with each other and providing a first output signal .phi.1, said first output signal .phi.1 rising in synchronism to the leading edge of said input clock signal .phi., assuming a floating state after the lapse of a predetermined period of time falling in synchronism to the trailing edge of said input clock signal .phi., and a second output signal .phi.2, said second output signal .phi.2 falling in synchronism to the occurrence of the floating state of said input signal .phi.1 and rising in synchronism to the trailing edge of said input clock signal .phi., a transistor circuit including a first and a second enhancement type transistor cascade connected between a V.sub.DD and a V.sub.SS power supply terminal, said first output signal .phi.1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistor, said second output signal .phi.

Abstract: A clock generator for producing a two phase output comprises a bistable circuit having two stages. The output of each stage is cross coupled to the input of the other and each cross coupling path includes a high-resistance transfer gate. Each transfer gate forms part of an RC delay element which is so arranged that at a transition of clock signals the output of one of the stages completes its transition substantially at the same time as the output of the other stage begins its transition. This results in non-overlapping outputs from the generator.

Abstract: A clock generator circuit (10) receives an input signal PPC.0. and generates a delayed clock output signal PC.0.. The circuit (10) is set to an initial condition by a precharge signal PC.0.R prior to a transition of the input signal PPC.0.. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC.0. produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC.0. to be driven from an initial low voltage state to the power supply voltage V.sub.cc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

Abstract: A voltage compatible circuit for providing TTL and CMOS level inputs and/or outputs is provided. An input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal. One or more input buffers and/or output buffers is coupled to the CMOS and TTL mode signals. The input buffers are responsive to input signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. The output buffers provide output signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. A reference voltage portion and a bias generator portion are coupled to the input and output buffers to provide the predetermined voltage levels.

Abstract: An enhancement-mode field effect transistor (ENFET) logic circuit providing greater fan-out capability. The logic circuit employs a conventional common-source inverter section, but additionally incorporates a current-driving section which drives the common-source inverter section. A current-driven inverter logic circuit is realized by employing a second ENFET transistor to drive the gate of the common-source inverter section. A current-driven NOR gate is realized by employing two ENFET transistors in parallel which drive the common-source inverter section. Also a current-driven NAND gate is realized by utilizing a single transistor having two gate inputs to drive the common-source inverter section. The use of sweep-out circuitry allows for control of the operational speed of the device. The logic circuit designs have high fan-out capability compared to the common-source inverter circuit alone.

Abstract: A device for generating a geometric sequence of values of an electrical quantity (charge or voltage) with the aid of switched capacitances. A switch control means operates a plurality of switches in a predetermined time pattern so as to distribute electric charges on a plurality of capacitors. A geometric sequence of electric charges is thus stored on the capacitors in which, first-order errors caused by inaccuracies in the capacitance values of the capacitors are eliminated. Furthermore, methods are proposed to minimize the influence of inevitable stray capacitances in the arrangement.

Abstract: A TTL fundamental logic circuit comprising an npn-type input transistor, an npn-type output transistor, and a pnp-type output transistor. The pnp-type output transistor has an emitter connected to the collector of the npn-type output transistor, a base connected to the base of the npn-type output transistor and a collector that is grounded. The pnp-type output transistor is turned on when the npn-type output transistor is turned off, thereby the potential of the high level output signal is decreased, and the propagation delay of the fundamental logic circuit is reduced.

Abstract: The present invention provides a circuit comprising (1) a logic element responsive to data of first and second negative voltage potentials, the logic element having a depletion mode MESFET data input gate, and (2) a depletion mode MESFET transmission gate operatively associated with the data input gate for enabling the selective serial transmission of data therethrough to the logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage of the data input gate being between approximately the first and second negative voltage potentials, the pinch-off threshold voltage of the transmission gate being between approximately the third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more

Abstract: A digital synchronizer includes a latch connected to a level sensitive circuit. The latch is constructed to provide a rapid transition between logic "0" and logic "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from logic "0" to logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for 3/4 of a machine cycle to allow any transients conditions within the latch to dampen out.

Abstract: An inverter circuit which comprises a load transistor (Q.sub.1) and a driving transistor (Q.sub.2) is connected in series between first and second power supplies (V.sub.ss, V.sub.pp). At least one transistor (Q.sub.3) for reducing the load of the load transistor is connected between the load transistor and the second power supply (V.sub.pp). A bootstrap circuit is connected to the gate of the transistor (Q.sub.3) and the gate potential of the transistor (Q.sub.3) is raised to a potential level higher than that of the second power supply (V.sub.pp).

Abstract: A circuit for providing a signal which enables the high impedance state of a subsequent three state circuit includes a first circuit portion which provides current to an output node to disable the high impedance state when an input signal is in the first state and a second circuit portion which sinks current from the output node to enable the high impedance state when the input signal is in a second state. The circuit includes an input stage which is directly coupled to a transistor, which transistor simultaneously enables said second circuit portion and disables said first circuit portion when the input signal switches from said second state to said first state.

Abstract: In the present invention, channel charge compensation is achieved in a MOS switch comprising two MOSFETs connected in parallel and a compensating MOSFET placed on the semiconductive substrate in precise symmetry with the two switching FETs, each of the FETs being designed to have the same channel charge storing capacity. Accordingly, first order variations in oxide thickness or in gate width across the surface of the semiconductive substrate do not affect the accuracy with which channel charge is compensated in the invention. The compensating FET is switched in complementary fashion with the two switching FETs so that it absorbs one-half of the channel charge expelled from the switching FETs when they are turned off, thus preventing this charge from upsetting other components in the circuit such as precision storage capacitors connected to the switch.

Abstract: A fuel injection system employing digital logic to generate injection command pulses of a time duration calculated to provide a precise quantity of fuel to meet presently existing, varying engine requirements is disclosed herein. The system employs a first or injector selection circuit operative to select an injector or injector group for injection and a second or adaptive delay circuit to generate an injection command. The circuits are electronically intercoupled to provide for substantially simultaneous application of the selection pulse and injection pulse to the proper injector group and to eliminate the need for a mechanical distributor arrangement to select the proper injector group. The time duration or delay signal is generated by a function generator producing an output as a known function of time with injection occurring during the time it takes for the output to reach a pre-determined, selected, threshold value.