Abstract: A voltage dropping element is connected in series with the conduction paths of first and second IGFETs, of complementary conductivity, between first and second terminals coupled to first (e.g. 5 volts) and second (e.g. 0 volt) voltage levels, respectively. The gates of the IGFETs are connected to an input terminal to which is applied TTL level signals (e.g. 0.4 to 2.4 volts) and their drains are connected to an output node. When the "high" TTL level (e.g. 2.4 volt) is present, the voltage dropping element reduces the effective gate-to-source voltage (V.sub.GS) of the first IGFET, reducing its conductivity, increasing its effective impedance substantially, and enabling the second IGFET to drive the output node to the second voltage level with little power dissipation. When the "low" TTL input (e.g. 0.4 volt) is present, the second IGFET is turned-off while the first IGFET is turned-on, driving the output node to the voltage at the first power terminal less the voltage drop of the voltage dropping element.

Abstract: As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

Abstract: A fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET. The bipolar transistor is driven into conduction by residual charge in the gate to source capacitance of the FET upon turn-off of the latter due to removal of gate drive. Conduction of the bipolar transistor provides faster discharge therethrough of the FET gate, whereby to facilitate faster FET turn-off without reverse gating current and its attendant auxiliary power supply.

Abstract: A bootstrap driver circuit is used asynchronously in a static RAM. A capacitor is coupled between second and third nodes, and a charge pump is coupled to provide charge to the second node. Address bits can be applied to the gates of respective transistors whose drains form a common node coupled to the source of a low impedance transistor whose drain is coupled to a first node. An inverter is coupled to the common node for applying a delayed input signal to the gates of first and second enhancement mode transistors. This provides a discharge path for the third node in response to a low level memory address signal thereby to maintain a differential voltage across the bootstrap capacitor. Also disclosed is an input protection circuit when the bootstrap driver is used as a chip select buffer. A timing circuit receives an input signal and develops a first signal and a delayed signal, both of which are applied to the bootstrap driver.

Abstract: In order to obtain a low as possible generator internal resistance, a first inverter (IV1) is arranged between the first and the third potential (U1, U3), and the switching section of a second inverter (IV2) is connected to the zero point of the circuit and to the output of the first inverter (IV1) which is modified in such a way that between the switching sections of its two transistors (T21, T22) there is inserted an intermediate transistor (MT). The point connecting the switching sections of the intermediate transistor (MT) and of the other transistor (T22) of the second inverter (IV2) is the output of the selection circuit and is arranged, via the switching section of an additional transistor (ZT) to the second potential (U2).

Abstract: A trigger circuit including arm and trigger comparators which are responsive to the push-pull output from a differential amplifier but insensitive to its common mode component. A controllable hysteresis insertion circuit is also included in the circuit for noise rejection and sensitivity control purposes.

Abstract: The network connections of the channels of complementary symmetry MOS FET's in a logic gate or array are altered electrically to program different logic responses to logic inputs. To this end, certain of the FET's are gate-injection or substrate-injection MOS FET's.

Abstract: A gallium arsenide buffer amplifier for use in a very large scale integrated circuits is provided. The transistor device in the buffer amplifier has a uniform depth N+ source, gate and drain region and the N+ dopant concentration is made very high which effectively reduces the resistance of the transistor device and permits the area of the device to be reduced by more than one order of magnitude while maintaining high current and power levels.

Abstract: Integrated digital MOS-semiconductor circuit, including a first circuit part for generating charging and switching pulses, a second circuit part having an input connected to the first circuit part for being addressed by the pulses supplied by the first circuit part, first, second and third self-locking MOS-field effect transistors each having a source, a drain and a gate electrode, first and second capacitors having first and second terminals, the first terminal of the first capacitor being connected through the first transistor to the input of the second circuit part, the first terminal of the second capacitor being connected through the second transistor to the input of the second circuit part, a first supply potential source at reference potential, a second supply potential source different from reference potential being connected to at least one terminal of the third transistor and through the third transistor to the first terminal of the second capacitor, the second supply potential source also being con

Abstract: A sense amplifier wherein each of a first through a fourth inverter comprises a driving transistor and a load transistor; the first, second, third and fourth inverters are interconnected in such a way that the outputs of the first and second inverters are applied to the third and fourth inverters, respectively; the first and second inverters have input terminals while the third and fourth inverters have output terminals; one terminal of each of the first through fourth inverters is connected to first power supply while the other terminals of the first and second inverters are connected directly or through a control transistor to second power supply; and the outputs from the first and second inverters are applied to the other terminals of third and fourth inverter, respectively.

Abstract: The decode circuit utilizes NPN and PNP transistors and performs a complete decode function in only one logic level with the no need for a true/complement input of each binary input. A first embodiment of the decoder provides an UP level output when selected. A second embodiment of the decoder provides a DOWN level output when selected. The decode circuit may be used as an address decode circuit in a memory and also portion(s) of the decode circuit may be used independently as a binary logic circuit. Also disclosed is a complementary current switch logic circuit with dual phase outputs.

Abstract: An active pull-up circuit is provided which is process compensating. The active pull-up circuit contains a voltage reference which drives a source follower. The inverting output of the source follower controls a pull-up device which is in parallel with an active pull-up device. The active pull-up device can be much smaller in size since it is now assisted by the controlled pull-up device. The controlled pull-up device is held off until the active pull-up device pulls up the bus or line connected to the active pull-up circuit to a predetermined voltage level.

Abstract: A logic circuit using depletion-mode field effect switching transistors, wherein, a plurality of logic elements respectively having at least one depletion-mode switching FET are connected in series. The source electrodes of the switching FETs are maintained at a voltage higher by a predetermined voltage than ground potential by the Schottky diode and connected commonly to each other. The switching FETs are connected at the drain electrodes through active loads to a power source terminal supplied with one type of external DC power source voltage. The drain potential of the switching FETs is level-shifted to a predetermined voltage higher than the gate potential of the FETs in the next stage. The FETs are provided between the diodes and ground to prevent the variation in the level shift voltage.

Abstract: A self-substrate-bias circuit device comprising substrate of P conductivity type, a capacitor element of MOS construction formed in said semiconductor substrate and whose one end is connected to the output terminal of a pulse generator, a diode element formed in said semiconductor substrate and connected between the other end of said capacitor element and a ground potential, and an P.sup.+ region of P conductivity type formed in the region of said seminconductor substrate which is contacted to said capacitor element and having higher impurity concentration than that of said semiconductor substrate.

Abstract: A bidirectionally source stacked FET circuit is provided with drain-referencing of the gating circuitry, instead of source-referencing. This requisite gate to source potential to charge the gate and effect conduction of the FETs is provided by referencing the gate circuitry to a common anode point of diodes having their cathodes connected to the drains of the FETs. The common anode point is at substantially the same potential as the common source point of the FETs. The gate charging potential is provided by current from a current source through a resistor to the common anode point, which IR drop establishes the requisite gate voltage to drive the corresponding FET into conduction regardless of the polarity of first and second main terminals at respective FET drains.

Abstract: A three-output level logic circuit comprises an output stage and a drive stage for driving the output stage. The output stage includes first and second MOS transistors connected in series between first and second power sources and a terminal is provided for producing three-state output signals. The drive stage includes third to sixth MOS transistors connected in series between the first and second power sources. A terminal is provided for supplying a data signal to the fourth and fifth MOS transistors. A control signal is supplied in common to the gate electrodes of the third to sixth MOS transistors. The conductivity types of the first to sixth MOS transistors are selected to operate the logic circuit with one control signal input and one data signal input.

Abstract: A multiplexer circuit is disclosed, for use with such signal sources as focal plane detector arrays, which contains a large number of parallel branches, each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier. The amplifier in each branch receives high impedance voltage signals originating from its individual detector and converts them with high power gain into current signals which feed into the common output line whenever the switch in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a signal IC chip which provides CMOS logic.

Abstract: A noninverting amplifier circuit for one propagation delay complex logic gates. The noninverting amplifier circuit is compatible with field effect transistor logic, including depletion-mode Schottky barrier field effect transistor (MESFET) inverting logic, gates. The basic noninverting amplifier circuit, utilizes field effect transistors (FET) and diodes, and comprises input interface means for receiving an input voltage signal, amplifier means for providing noninverted amplification of the input voltage signal, and buffer means for driving, and shifting the voltage level of the amplified input voltage signal. In another embodiment, additional circuit means for enabling performance of the "AND" logic function is included in the basic noninverting amplifier circuit. In a third embodiment, additional circuit means for enabling performance of the "OR" logic function is included in the basic noninverting amplifier circuit.

Abstract: Disclosed is a semiconductor integrated circuit device, which comprises at least one selection circuit including a first node, a first MOS transistor for periodically pre-charging the first node, second MOS transistors for determining the potential state of the first node in response to a state designating signal, a third MOS transistor connected to the first node and functioning as a barrier, a second node connected through the barrier MOS transistor to the first node, a fourth MOS transistor for providing a signal at a level corresponding to the potential state of the second node, and a control circuit for holding the gate potential of the barrier MOS transistor at a low level for a period from the instant when the potential state of the first node is determined till the subsequent pre-charge cycle.

Abstract: An integrated injection logic circuit includes a plurality of integrated injection logic gates each having a PNP transistor for injector and NPN transistor for signal inversion, and an injector common line to which the respective injector PNP transistors are commonly connected. A test pad for electric probing is provided at least one location of the injector common line.