Abstract: A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of only two gate delays and requiring a total of only nine transistors. Another embodiment of this invention is a Tri-State circuit constructed utilizing a single NOR gate (84), a single inverter (83), a single N channel transistor (88), and two P channel transistors (86, 87). In this embodiment of my invention, a total of nine MOS transistors are required, and the propagation delay between the input terminal and the output terminal is equal to two gate delays.

Abstract: The three state input circuit includes a P channel MOS FET and an N channel MOS FET which are supplied with an input signal at their drain electrodes, and a pair of flip-flop circuits connected to source electrodes of respective FETS and acting as a memory. Gate electrodes of the FETs are supplied with timing signals. The circuit operates to sequentially and periodically judge the input states in accordance with the timing signals, and then the stores results of such judgements and then outputs the stored results as 2 bit binary signals.

Abstract: A circuit for controlling signals between a signal source at a first terminal, a device under test at a second terminal and a metering means at a third terminal where the device under test may be either a source of signals or a load, provides signals at the first terminal to the second terminal and to the third terminal in one condition and in a second condition provides signals from the second terminal to the third terminal and isolates the first terminal from signals at the second terminal.

Abstract: A current responsive sense amplifier circuit is used in a semiconductor memory. The circuit includes means for reducing the voltage swings that are associated with the binary logic states.

Abstract: A differential current sense amplifier is shown suitable for high speed semiconductor memory sensing. A reference current generation circuit is also developed for operating a plurality of sense amplifiers.

Abstract: A logic gate section of a Schmitt trigger circuit has first and second nodes to which variable bias voltages are applied. A first bias control IGFET is connected between the first node and a first potential terminal. A second bias control IGFET is connected between the first node and a second potential terminal. A third bias control IGFET is connected between the second node and the first potential terminal. A fourth bias control IGFET is connected between the second node and the second potential terminal. A control signal to the gates of the first and fourth bias control IGFET's is provided by the Schmitt trigger input signal and the control signal to each of the gates of the third and fourth bias control IGFET's is provided by the Schmitt trigger feedback connection of two series-connected inverters.

Abstract: A buffer circuit is provided wherein bipolar transistors are connected to the output terminal of an IIL gate. The buffer circuit includes an IIL gate having a plurality of output terminals. The output terminals of the IIL gate are respectively connected to the bases of the bipolar transistors of which the emitter-collector paths are connected in series between a buffer output terminal and a reference voltage terminal.

Abstract: A circuit for detecting a difference in the relative magnitudes of two voltages includes a current sensing circuit connected between the first voltage and ground to thereby cause a first current to flow in the current sensing circuit, an amplifier connected between the second voltage and ground and connected to the current sensing circuit to thereby cause a second current to flow, the second current being equal to the first current when the first voltage is equal to the second voltage, and a variable impedance inverter connected to the first voltage and connected to the amplifier, the variable impedance being controlled by the first voltage, the output of the inverter thereby being related to the difference between the first voltage and the second voltage. The invention is particularly useful for controlling a battery backup power supply in a microprocessor having a volatile memory and for creating precision delay circuits.

Abstract: A controllable impedance means is connected in series with the conduction path of transistors forming a complementary inverter for selectively "skewing" the inverter in a direction to center its toggle point with respect to the signals applied to the inverter input. The "skewed" inverter is thereby compensated for offsets or asymmetry in its input signals. Also disclosed is the use of skewed inverters to form memory cells which can be easily written to both binary conditions. Also disclosed is the use of the controllable impedances as "cross-unders" to enable the fabrication of very compact "skewable" inverters and memory cells.

Abstract: Drift in the zero or datum reference point of a circuit (such as that forming part of a measuring device) is corrected by sensing the rate of change of the signal provided by the circuit and distinguishing between a rate of change characteristic of that due to a valid signal indicative of a measurement and a rate of change characteristic of that due to drift in the circuit.In one embodiment, a window comparator 18 senses the rate of change of the signal output from circuit 10 by periodically sampling in sample/ hold 16 and then comparing with the current value of the signal. A signal circulating path 20, 21, 22 holds a drift compensating value which is updated when comparator 18 senses a rate of change below a threshold value which is indicative of drift in circuit 10. The drift compensating value is added to the signal from circuit 10 in summing amplifier 15 thereby correcting the signal for drift.

Abstract: A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken.

Abstract: A pair of CMOS inverters are cross coupled in a latching configuration. Both inverter supply terminals are coupled to complementary toggles that can render the inverters operative or inoperative. First, the inverters are rendered inoperative. An output switch is coupled between the output nodes so that the inverter's output nodes can be driven to the same potential, thus canceling any offset voltage. An input switch produces sampling over a time interval that extends beyond the output switch on period. After the sampling period, the toggles are operated to turn the inverters on and to produce a latch state determined by the potential change present in the sampling interval.

Abstract: A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Abstract: A Schmitt circuit comprises a series connection of a first, second and third MOS transistors connected between a voltage source and the ground, and a fourth MOS transistor connected between the voltage source and the junction of the second and third MOS transistors. An input voltage is applied to the gates of the second and third MOS transistors. The voltage at the junction of the first and second MOS transistors is applied to the gate of the fourth MOS transistor and is also led out as an output. The Schmitt circuit further comprises a series connection of a sixth and seventh MOS transistors connected between the voltage source and the ground for dividing the source voltage, and a fifth MOS transistor connected between the junction of the sixth and seventh MOS transistors and the junction of the first and second MOS transistors and adapted to be rendered conductive when the potential at the said junction exceeds a predetermined voltage.

Abstract: Switch with at least two series-connected MOS-FETs has a drain terminal of a preceding MOS-FET connected to a source terminal of a succeeding MOS-FET the MOS-FETs having respective control terminals connectible to a control voltage. The control terminal of the preceding MOS-FET is directly connected to a terminal of the control voltage source. The control terminal of the succeeding MOS-FET is connected to the control terminal of the respective preceding MOS-FET via a diode poled in forward direction with respect to the control voltage source. A resistor is connected between the control terminal and the source terminal of the succeeding MOS-FET.

Abstract: A sense amplifier quickly charges a column line to a first predetermined voltage level with first, second and third transistors and then charges the column to a second predetermined voltage by using only the second and third transistors. The second and third transistors continue charging to the second predetermined voltage by virtue of having a lower threshold voltage than the first transistor. If a selected memory cell in the column is in a conducting state, the column charges to only the first predetermined voltage for detection as a logic "0". If the selected memory cell in the column is in a non-conducting state, the column continues charging to the second predetermined voltage for detection as a logic "1".

Abstract: In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

Abstract: A programmable logic device is disclosed which contains additional circuitry allowing the architecture to be programmed. Operating as an input circuit or as an output circuit, the logical function of the device is selected to operate as a buffer, latch or register. When fabricated as a portion of a programmable logic array, the architecture is modified to the desired configuration by fusible connections which conduct normal operating current until overloaded by selective programming. Thereafter, the data path through the array is programmed in a normal fashion. The programmable architecture circuitry is readily fabricated in an integrated circuit form in conjunction with a programmable logic array.

Abstract: A Transistor-Transistor Logic (TTL) gate is disclosed wherein a different amount of base current is applied to the inverter transistor than is applied to the base of the output transistor. In one embodiment, a current mirror circuit controls the amount of base current flowing between the input transistor collector terminal and the base terminal of the inverter transistor to an amount less than that flowing between the input transistor collector terminal and the base terminal of the output transistor. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.

Abstract: A level sensitive switching circuit particularly useful as a data detecting sense amplifier for a Read-Only Memory integrated circuit. The switching circuit includes a pair of IGFET inverter circuits coupled between a drain supply voltage and a common voltage node. The signal to be sensed is applied to the input of the first inverter, the output of which is the circuit output. Two feedback loops are established between the output of the first inverter and the source electrode of an IGFET input device in the first inverter. The first feedback loop includes a source follower responsive to the output of the first inverter and the second feedback loop includes the second inverter having its output coupled to the gate of one of two series-connected devices between the common voltage node and the source supply voltage. The other series-connected device is responsive to an amplifier set clock pulse to selectively enable the circuit.