Abstract: An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

Abstract: A micro device includes an epitaxial structure, an insulating layer, and a light-transmissive layer. The epitaxial structure has a top surface and a bottom surface opposite to each other and a peripheral surface connected to the top surface and the bottom surface. The insulating layer covers the peripheral surface and the bottom surface of the epitaxial structure and exposes a portion of the peripheral surface. The light-transmissive layer covers the top surface of the epitaxial structure and is extended over at least a portion of the portion of the peripheral surface.

Abstract: A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Abstract: A light emitting diode device with flip-chip structure includes a transparent protective substrate, a transparent conductor layer, a glue layer, a group III-V stack layer, a first conductivity metal electrode, a second conductivity metal electrode and an insulating layer. The transparent conductor layer is formed on the transparent protective substrate. The glue layer bonds the transparent protective substrate and the transparent conductor layer. The group III-V stack layer and the first conductivity metal electrode are respectively formed on a first portion and a second portion of the transparent conductor layer. The second conductivity metal electrode is formed on a portion of the group III-V stack layer. The insulating layer covers exposed portions of the transparent conductor layer and the group III-V stack layer, and the insulating layer further covers portions of the first and second conductivity metal electrodes, so as to expose the first and second conductivity metal electrodes.

Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.

Abstract: A semiconductor device package that incorporates a waveguide usable for high frequency applications, such as radar and millimeter wave is provided. Embodiments employ a rigid-flex printed circuit board structure that can be folded to form the waveguide while, at the same time, mounting one or more semiconductor device die or packages. Embodiments reduce both the area of the mounted package and the distance signals need to travel between the semiconductor device die and antennas associated with the waveguide.

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

Abstract: A display device includes a substrate, a thin film transistor disposed on the substrate, and a display element electrically connected to the thin film transistor. The substrate includes a first substrate layer, a second substrate layer disposed on the first substrate layer, a first barrier layer disposed between the first substrate layer and the second substrate layer, and a first ultraviolet light blocking layer disposed between the first substrate layer and the second substrate layer.

Abstract: A method for manufacturing a laterally diffused metal oxide semiconductor device and a semiconductor device are provided. A body region is formed before forming a gate dielectric layer and a gate conductor, thereby reducing a channel length of the semiconductor device, thus reducing the on-resistance. In addition, a drift region serves as both a region withstanding a high voltage and a diffusion suppression region for suppressing lateral diffusion of the body region, thereby further reducing the channel length of the semiconductor device, thus manufacturing a short-channel semiconductor device.

Abstract: A semiconductor device including a stacked body that includes insulating layers and conductive layers that are alternately stacked, a first film provided inside a recess portion that penetrates through the stacked body, a second film provided on a surface of the first film, a third film provided on a surface of the second film, and a fourth film provided on a surface of the third film. An average concentration of a halogen element per unit area in the third film and the fourth film is lower than an average concentration of the halogen element per unit area at an interface between the third film and the fourth film.

Abstract: Provided is an image sensor including a semiconductor substrate having a first surface and a second surface opposite each other, an organic photoelectric conversion device on the first surface of the semiconductor substrate, a through electrode structure connected to the organic photoelectric conversion device, and a pixel separation structure extending from the first surface toward the second surface of the semiconductor substrate. The semiconductor substrate may include a photoelectric conversion region in the semiconductor substrate. The pixel separation structure may surround the photoelectric conversion region when viewed in plan. The pixel separation structure may include a separation conductive pattern and a first sidewall dielectric pattern. The first sidewall dielectric pattern may continuously extend from between the separation conductive pattern and the semiconductor substrate to between the semiconductor substrate and a sidewall of the through electrode structure.

Abstract: A light emitting device package disclosed to an embodiment of the invention includes a body including an upper surface and a lower surface, the body including a first recess and a second recess concaved from the lower surface toward the upper surface; a light emitting device disposed on the body and including a first bonding portion and a second bonding portion; and first and second conductive portions respectively disposed in the first recess and the second recess, wherein the body includes a first through hole and a second through hole penetrating an upper surface of each of the first recess and the second recess and the upper surface of the body, and wherein each of the first and second conductive portions extends into the first and second through holes and is electrically connected to the first bonding portion and the second bonding portion, respectively.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: The present invention discloses a flip-chip LED chip used in a backlight and a producing method thereof. The flip-chip LED chip used in the backlight comprises a substrate, an epitaxial layer, a transparent conductive layer, an insulating layer, a first reflecting layer, a second reflecting layer, a first electrode, and a second electrode. In the present invention, the first reflecting layer and the second reflecting layer are formed on both sides of the substrate. By adjusting the reflectance of the first reflecting layer and the second reflecting layer, the light emitted by the epitaxial layer is reflected by the first reflecting layer and the second reflecting layer, resulting in 20-40% of the light being emitted from the back of the chip, and 60-80% of the light being emitted from the side of the chip. This increases the light uniformity of the LED backlight.