Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.

Abstract: A processing system and method for chemical oxide removal (COR), wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.

Abstract: A method includes connecting together one or more anode connection members of one or more anode foils and one or more cathode connection members of one or more cathode foils and electrically isolating the one or more anode foils from the one or more cathode foils. A capacitor stack includes a plurality of cathode layers having cathode connection members and a plurality of anode layers having anode connection members. The anode connection members are connected to the cathode connection members and configured such that the anode layers can be electrically separated from the cathode layers by cutting only the anode connection members or the cathode connection members.

Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

Abstract: A method of making and a high performance reworkable heatsink and packaging structure with solder release layer are provided. A heatsink structure includes a heatsink base frame. A selected one of a heatpipe or a vapor chamber, and a plurality of parallel fins are soldered to the heatsink base frame. A solder release layer is applied to an outer surface of the heatsink base frame. The solder release layer has a lower melting temperature range than each solder used for securing the selected one of the heatpipe or the vapor chamber, and the plurality of parallel fins to the heatsink base frame. After the solder release layer is applied, the heatpipe or the vapor chamber is filled with a selected heat transfer media.

Abstract: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

Abstract: A thermal enhanced structure comprising a packaged electronic device and a heat sink that is removably attached thereto. The thermal enhanced structure includes a plastic ball grid array (PGBA) with an electronic chip, a plastic mold cover, and a heat spreader with a plurality of spaced apart securing studs positioned and caulked at a periphery edge thereof. The mold cover, the heat spreader and studs are molded and embedded with one another to form a single unit with improved torque strength and heat dissipation. The single molded unit and the plastic ball grid array are secured together by an adhesive material. Then the heat sink can be easily and removably attached to the molded single unit by fastening elements to the molded studs, thereby allowing more efficient controllable forces or pressures to be applied as the mechanical fastening elements are removably attached to the molded studs to thereby prevent stress and damage to the PBGA package.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.

Abstract: The lower end of a resin wall is bonded to a radiating plate, and a lead is fixed so as to extend through the resin wall. After a semiconductor chip is bonded thereto, a resin lid is put to seal the semiconductor chip. Recessed parts for burying the lower end of the resin wall are formed on the side parts of the radiating plate, and protruding parts are further provided within the recessed parts. The lead has holes formed on the package outer part and the resin wall inner part. The loading surface of the semiconductor chip is finished with silver plating, and the package exterior and the lead are plated with gold. The shape fitted to the resin wall is imparted to the resin lid, and the resin lid is further formed into a vertically plane symmetric shape.

Abstract: A method of manufacturing a thin film transistor includes: forming an amorphous silicon layer and a blocking layer; forming a photoresist layer having first and second photoresist patterns spaced apart from each other on the blocking layer; etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; reflowing the photoresist layer so the first and second photoresist patterns abut each other; forming a capping layer and a metal layer; removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer; etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and removing the first and second blocking patterns.

Abstract: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the surface of the semiconductor substrate from metal of the at least one metal-containing precursor. The invention also includes semiconductor constructions having metal-containing layers which include one or more of copper, cobalt, gold and nickel in combination with one or more of palladium, platinum, iridium, rhodium and ruthenium.

Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.

Abstract: An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.

Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.

Abstract: A substrate processing apparatus and a substrate processing method are provided wherein an oxide film which is thinner than the conventional films can be formed with uniform thickness when forming an oxide film on the front-side surface of a substrate. A substrate processing apparatus (12) for processing a substrate (W) by feeding a processing liquid comprises: a temperature regulator (133) to regulate the temperature of said processing liquid; and a underplate temperature adjuster (115) to adjust the temperature of an underplate (77) which is placed in proximity to the backside surface of said substrate W.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.

Abstract: A method is disclosed for growing a nitrogen-containing III-V alloy semiconductor on a semiconductor substrate such as GaAs, which is formed by MOCVD method using nitrogen containing organic compounds having relatively low dissociation temperatures. The alloy semiconductor has a high nitrogen content which exceeds the contents previously achieved, and has a high photoluminescence intensity. There are also disclosed fabrications of semiconductor devices comprising the alloy semiconductors, such as heterostructure and homo-junction light emitting devices.