Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Abstract: An embedded semiconductor memory is fabricated by: forming diffusion bit line regions in a semiconductor substrate; then thermally oxidizing the upper surface of the substrate, thereby forming a bottom oxide layer over the substrate and simultaneously forming bit line oxide regions over each of the diffusion bit line regions; and then forming an intermediate dielectric layer (e.g., silicon nitride), over the bottom oxide layer and the bit line oxide regions. CMOS well implants are then performed in a CMOS section of the device through the silicon nitride layer and bottom oxide layer. The silicon nitride layer and bottom oxide layer are then removed in the CMOS section, and a top dielectric layer, such as a high-temperature oxide or a high-k dielectric, is deposited. The top dielectric layer completes a memory stack of the memory device, and forms a gate dielectric layer of a high voltage transistor in the CMOS section.

Abstract: A semiconductor device having interconnects is reduced in leakage current between the interconnects and improved in the TDDB characteristic. It includes an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, including a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118), and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.

Abstract: When a gettering sink is removed by using alkaline solution of etchant having a high selectivity to the gettering sink and a barrier film functioning as an etching stopper, residue of gettering is left. However, according to the present invention, a semiconductor film that serves as a gettering sink contains nitrogen at concentration of 1×1018 atoms/cm3 or lower, oxygen at concentration of 8×1019 atoms/cm3 or lower, and noble gas at concentration is of 1×1020 atoms/cm3 or higher. In order to achieve the above-described impurity concentrations, a concentration of oxygen that is an impurity element in a chamber is reduced by using a flammable gas for heating and exhausting oxygen.

Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. Interconnect system has the means, which could reduce the microwave loss by reducing the effective dielectric loss and dielectric constant of the interconnect system, and increase the bandwidth of the interconnects and also reduce the signal propagation delay, respectively. Ideally, the speed of the electrical signal on the signal line can be reached to speed of the light in the air, and the bandwidth can be reached to closer to the optical fiber. The interconnect systems consists of the signal line, dielectric system with opened trench or slot filled up with the air or lower dielectric loss material, and the ground plan. The signal line proposed in this invention could be made any type of signal line configuration for example, microstripline, strip line or coplanar line. The signal line can also be made as single ended or differential pairs of any configurations.

Abstract: A method of fabricating a single crystal thin film includes forming a non-single crystal thin film on an insulating base; subjecting the non-single crystal thin film to a first heat-treatment, thereby forming a polycrystalline thin film in which polycrystalline grains are aligned in an approximately regular pattern; and subjecting the polycrystalline thin film to a second heat-treatment, thereby forming a single crystal thin film in which the polycrystalline grains are bonded to each other. In this method, either the first heat-treatment or the second heat-treatment may be performed by irradiation of laser beams, preferably, emitted from an excimer laser. A single crystal thin film formed by this fabrication method has a performance higher than a related art polycrystalline thin film and is suitable for fabricating a device having stable characteristics. The single crystal thin film can be fabricated for a short-time by using laser irradiation as the heat-treatments.

Abstract: A boron phosphide-based semiconductor light-emitting device, comprising: a crystalline substrate; a first semiconductor layer formed on said crystalline substrate, said first semiconductor layer including a light-emitting layer, serving as a base layer and having a first region and a second region different from the first region; a boron phosphide-based semiconductor amorphous layer formed on said first region of said first semiconductor layer, said boron phosphide-based semiconductor amorphous layer including a high-resistance boron phosphide-based semiconductor amorphous layer or a first boron phosphide-based semiconductor amorphous layer having a conduction type opposite to that of said first semiconductor layer; a pad electrode formed on said high-resistance or opposite conductivity-type boron phosphide-based semiconductor amorphous layer for establishing wire bonding; and a conductive boron phosphide-based crystalline layer formed on said second region of said first semiconductor layer, said conductive b

Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: A method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing. Preferably, the second spacing placing the film of material in either a tensile or compressive mode across the entirety of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method includes processing the film of material to form a first region and a second region within the film of material. The first region and the second region are characterized by either the tensile or compressive mode. Preferably, both the first and second regions in their entirety are characterized by either the tensile or compressive mode.

Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the metallization is exposed in a window (301) opened through the thickness of the overcoat layer. The metal structure comprises a patterned conductive barrier layer (330) positioned on the copper metallization, wherein this barrier layer forms a trough with walls (331) conformal with the overcoat window. The height (331a) of the wall is less (between 3 and 20 %) than the overcoat thickness (320a), forming a step (340). A plug (350) of bondable metal, preferably aluminum, is positioned in the trough and has a thickness equal to the trough wall height (331a).

Abstract: A semiconductor device having high operating performance and reliability is disclosed, and its fabrication process is also disclosed. In an n-channel type TFT 302, an Lov region 207 is disposed, whereby a TFT structure highly resistant to hot carriers is realized. Further, in an n-channel type TFT 304 forming a pixel portion, Loff regions 217 to 220 are disposed, whereby a TFT structure having a low OFF-current value is realized. In this case, in the Lov region, the n-type impurity element exists at a concentration higher than that of the Loff regions, and the whole of the n-type impurity region (b) which constitutes the Lov region is sufficiently activated by optical annealing, so that a good junction portion is formed between the n-type impurity region and the channel forming region.

Abstract: A liquid crystal display includes a plurality of gate lines (GØ-Gn), a plurality of data lines (D1-Dn) formed in a direction crossing the gate lines, a plurality of pixel electrodes formed in a pixel area defined by the gate lines and the data lines, the pixel electrodes indicating pictures by a control of the corresponding gate lines, and a light volume adjusting layer formed on a lower layer of the pixel electrodes controlled by a second one of the gate lines (G1).

Abstract: Various kinds of metal elements existing on the surface of a wafer are analyzed with higher sensitivity. A high concentration HF solution is dropped onto a surface of a wafer. By providing the droplets of high concentration HF solution, the native oxide film on the surface of the wafer is dissolved into the solution, and the metal elements or compounds thereof existing in vicinity of the surface of the wafer are eliminated from the wafer and are incorporated into the high concentration HF solution. The droplets formed by agglomerating the high concentration HF solution are aggregated at a predetermined position on the surface of the wafer. Then, the recovered droplet of the high concentration HF solution is dried. The aggregated material is irradiated with X-ray at an angle for promoting total reflection, and the total reflection X-ray fluorescence spectrometry is conducted to detect the emitted X-ray.

Abstract: In the case of the method, an analysis is performed by using values of at least one process parameter of the manufacturing process of the physical object and, as a result of the analysis, when they satisfy a prescribed selection criterion, physical objects are marked in such a way that the associated physical objects can be taken as a random sample for the monitoring of the manufacturing process.

Abstract: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.

Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.