Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.

Abstract: An in-line, in-process or in-situ and non-destructive metrology system, apparatus and method provides composition, quality and/or thickness measurement of a thin film or multi-layer thin film formed on a substrate in a thin film processing system. Particularly, the subject invention provides a spectroscopic ellipsometer performing spectroscopic ellipsometry while the wafer is in a thin film processing system. In one form, the spectroscopic ellipsometer is associated with a wet bench system portion of the thin film processing system. The spectroscopic ellipsometer obtains characteristic data regarding the formed thin film to calculate penetration depth (Dp) for a thin film formed on the substrate. Particularly, the ellipsometer obtains an extinction coefficient (k) which is used to calculate penetration depth (Dp). Penetration depth (Dp), being a unique function of the extinction coefficient (k) provides the information for the composition, quality and/or thickness monitoring of the thin film.

Abstract: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.

Abstract: A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: An SOI wafer in which a base wafer and a bond wafer respectively consisting of silicon single crystal are bonded via an oxide film, and then the bond wafer is thinned to form a silicon active layer, wherein the base wafer is formed of silicon single crystal grown by Czochralski method, and the whole surface of the base wafer is within N region outside OSF region and doesn't include a defect region detected by Cu deposition method, or the whole surface of the base wafer is within a region outside OSF region, doesn't include a defect region detected by Cu deposition method, and includes I region containing dislocation cluster due to interstitial silicon. Thereby, there is provided an SOI wafer that retains high insulating properties and has an excellent electrical reliability in device fabrication even in the case of forming an extremely thin interlevel dielectric oxide film with, for example, a thickness of 100 nm or less.

Abstract: Systems and methods are described for controlled alignment of catalyticaly grown nanostructures in a large-scale synthesis process. A composition includes an elongated nanostructure including a first segment defining a first axis and a second segment coupled to the first segment, the second segment defining a second axis that is substantially nonparallel to the first axis. A method includes: generating an electric field proximate an edge of a protruding section of an electrode, the electric field defining a vector; and forming an elongated nanostructure located at a position on a surface of a substrate, the position on the surface of the substrate proximate the edge of the protruding section of the electrode, at least one tangent to the elongated nanostructure i) substantially parallel to the vector defined by the electric field and ii) substantially non-parallel to a normal defined by the surface of the substrate.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.

Abstract: Exemplary embodiments of the present invention provide a method of manufacturing a semiconductor device that can take a connection between layers without giving damage to a layer, which is underlying. The semiconductor device includes forming conductive members Ms and Md at a predetermined position of a semiconductor film, forming an insulating film on a whole surface of a substrate excluding the conductive members Ms and Md, and forming a conductive film that is connected to the semiconductor film with the conductive member Ms and Md.

Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the surface of the semiconductor substrate from metal of the at least one metal-containing precursor. The invention also includes semiconductor constructions having metal-containing layers which include one or more of copper, cobalt, gold and nickel in combination with one or more of palladium, platinum, iridium, rhodium and ruthenium.

Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.

Abstract: Disclosed herein is a wavelength converted light emitting apparatus comprising a substrate, a light emitting diode, and a phosphor layer. The substrate is formed at its upper surface with first and second conductive patterns. At a partial region of the first conductive pattern and at the second conductive pattern are formed first and second connection bumps, respectively. The light emitting diode has first and second surfaces opposite to each other, and a side surface. The first surface of the light emitting diode is formed with first and second electrodes. The light emitting diode is disposed at the upper surface of the substrate so that the first and second electrodes are connected to the first and second connection bumps, respectively. The phosphor layer is formed along the second surface and side surface of the light emitting diode by a certain thickness, thereby serving to convert a wavelength of light emitted from the light emitting diode.

Abstract: A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semiconductor substrate to form a conductive element when a plating solution is forced from the first side of the semiconductor substrate to the second side of the semiconductor substrate through the hole. The hole is plated in a generally planar plating topology from the first side to the second side of the semiconductor substrate. The through-hole conductor may be formed in a plating system where the semiconductor substrate forms at least a partial partition between a higher pressure bath and a lower pressure bath with the plating solution passing through the hole causing plating within the inner surface of the hole.

Abstract: A laser beam temporally modulated in amplitude by a modulator and shaped into a long and narrow shape by a beam shaper is rotated around the optical axis of an image rotator inserted between the beam shaper and a substrate. Thus, the longitudinal direction of the laser beam having the long and narrow shape is rotated around the optical axis on the substrate. In order to perform annealing in a plurality of directions on the substrate, the laser beam shaped into the long and narrow shape is rotated on the substrate while a stage mounted with the substrate is moved only in two directions, that is, X- and Y-directions. In such a manner, the substrate can be scanned at a high speed with a continuous wave laser beam modulated temporally in amplitude and shaped into a long and narrow shape, without rotating the substrate. Thus, a semiconductor film can be annealed.

Abstract: A light-emitting device having a structure in which a mask used for forming a film such as an organic compound layer does not come in contact with the pixels in forming the light-emitting elements, and a method of fabricating the same. In fabricating the light-emitting device of the active matrix type, a partitioning wall constituted by a second wiring and a separation portion is formed on the interlayer-insulating film, and the pixels are surrounded by the partitioning wall, preventing the mask from coming into direct contact with the pixels, the mask being used for forming the organic compound layer and the opposing electrode of the light-emitting elements.

Abstract: A method for fabricating an LED that radiates white spectrum light. A phosphor that radiates a white spectrum after excitation in the blue or UV spectrum is uniformly deposited onto a GaN epitaxial wafer prior to die separation and packaging. This allows wafer-level processing and probing of white LEDs and produces true white LED chips.