Patents Examined by Laura Menz
  • High mobility devices with anti-punch through layers and methods of forming same
    Patent number: 9548362
    Abstract: An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • Semiconductor device and method for manufacturing the same
    Patent number: 9548397
    Abstract: An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: January 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tatsuya Honda
  • Integrated circuit with dual stress liner boundary
    Patent number: 9543437
    Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Youn Sung Choi, Greg Charles Baldwin
  • Electrode materials and interface layers to minimize chalcogenide interface resistance
    Patent number: 9543515
    Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: F. Daniel Gealy, Andrea Gotti, Davide Colombo, Kuo-Wei Chang
  • Monitor structures and methods of formation thereof
    Patent number: 9530720
    Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Tobias Herzig
  • Semiconductor devices having metal gate and method for manufacturing semiconductor devices having metal gate
    Patent number: 9530778
    Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Chih-Kai Hsu, Li-Wei Feng, Shih-Hung Tsai, Chien-Ting Lin, Jyh-Shyang Jenq, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen
  • Method and system for three-dimensional (3D) structure fill
    Patent number: 9530674
    Abstract: Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 27, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Ellie Yieh, Ludovic Godet, Srinivas Nemani, Er-Xuan Ping, Gary Dickerson
  • High throughput laser processing
    Patent number: 9527164
    Abstract: A solar cell is formed using a solar cell ablation system. The ablation system includes a single laser source and several laser scanners. The laser scanners include a master laser scanner, with the rest of the laser scanners being slaved to the master laser scanner. A laser beam from the laser source is split into several laser beams, with the laser beams being scanned onto corresponding wafers using the laser scanners in accordance with one or more patterns. The laser beams may be scanned on the wafers using the same or different power levels of the laser source.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 27, 2016
    Assignee: SunPower Corporation
    Inventors: Gabriel Harley, Thomas Pass, Peter John Cousins, John Viatella
  • Light emitting device
    Patent number: 9525115
    Abstract: A light emitting device includes a substrate, metallization, a light emitting element, conducting wire, light reflective resin, and insulating material. The metallization is provided on a surface of the substrate that is made of insulating substance. The light emitting element is mounted on the substrate. The conducting wire electrically connects the metallization and the light emitting element. The light reflective resin is provided on the substrate to reflect light from the light emitting element. The insulating material covers at least part of metallization surfaces. The insulating material is established to come in contact with a side of the light emitting element.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: December 20, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Mototaka Inobe, Motokazu Yamada, Kazuhiro Kamada
  • Gas and moisture permeation barriers
    Patent number: 9525155
    Abstract: A gas and moisture permeation barrier stack deposited by both sputtering and atomic layer deposition techniques. In one embodiment, the barrier stack comprises a bottom barrier layer deposited on a substrate by sputtering and a top barrier layer deposited on the sputtered layer by atomic layer deposition. In one embodiment, the sputtered barrier layer has a water vapor transmission rate of about 10?5 gm/m2·day or lower, and the top barrier layer improves the water vapor transmission rate of the resulting two-layer barrier stack to about 10?6 gm/m2·day or lower.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 20, 2016
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Xianghui Zeng, Lorenza Moro, Damien Boesch
  • Insulated gate switching element
    Patent number: 9525062
    Abstract: An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate electrode disposed on the gate insulating film. The semiconductor substrate includes a first semiconductor region, a base region, and a second semiconductor region. The gate electrode faces the base region with the gate insulating film interposed therebetween. A high-resistance region, which is separated from the gate insulating film and has higher resistance to a number of carriers of a first conduction type semiconductor than that of the base region, is disposed in at least one of a first interface which is an interface between the base region and the first semiconductor region and a second interface which is an interface between the base region and the second semiconductor region.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: December 20, 2016
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takashi Ishida, Takashi Okawa
  • Semiconductor device and manufacturing method thereof
    Patent number: 9524906
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 20, 2016
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jong Sik Paek, Eun Sook Sohn, In Bae Park, Won Chul Do, Glenn A. Rinne
  • Reduced area power devices using deep trench isolation
    Patent number: 9525060
    Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Sameer Pendharkar, Seetharaman Sridhar
  • Semiconductor integrated circuit device
    Patent number: 9515076
    Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Nii
  • OLED encapsulated in a full-wafer adhesive having a perforated cover
    Patent number: 9515293
    Abstract: The invention relates to an organic light-emitting diode (OLED) comprising a stack comprising, in sequence and in the following order, a substrate (2), a first electrode (3), an organic layer (4), and a second electrode (5), characterized in that it comprises a layer of adhesive (6) and a cover (7) fixed onto said stack using said layer of adhesive (6), and the cover (7) comprises at least one through-opening (8), wherein electrical access to an electrode (3, 5) is possible through said opening (8). The present invention can be more specifically used in electronic devices having screens and lighting.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: December 6, 2016
    Assignee: Astron Flamm Safety Sarl
    Inventors: Bruno Dussert-Vidalet, Mohamed Khalifa, Claire Vacher
  • Laser welding transparent glass sheets using low melting glass or thin absorbing films
    Patent number: 9515286
    Abstract: A method of sealing a workpiece comprising forming an inorganic film over a surface of a first substrate, arranging a workpiece to be protected between the first substrate and a second substrate wherein the inorganic film is in contact with the second substrate; and sealing the workpiece between the first and second substrates as a function of the composition of impurities in the first or second substrates and as a function of the composition of the inorganic film by locally heating the inorganic film with a predetermined laser radiation wavelength. The inorganic film, the first substrate, or the second substrate can be transmissive at approximately 420 nm to approximately 750 nm.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 6, 2016
    Assignee: Corning Incorporated
    Inventors: Leonard Charles Dabich, II, Stephan Lvovich Logunov, Mark Alejandro Quesada, Alexander Mikhailovich Streltsov
  • Wafer level overmold for three dimensional surfaces
    Patent number: 9508566
    Abstract: Embodiments of the invention include a method for shaping a flexible integrated circuit to a curvature and the resulting structure. A flexible circuit is provided. An epoxy resin and amine composition is deposited on the flexible integrated circuit. The deposited epoxy resin and amine composition is B-staged. The flexible integrated circuit is placed within a mold of a curvature. The B-staged epoxy resin and amine composition is cured subsequent to placing the flexible integrated circuit within the mold of the curvature.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Paul S Andry, Bing Dang, Eric P Lewandowski, Jae-Woong Nah, Bucknell C Webb
  • Organic light emitting diode display and manufacturing method thereof
    Patent number: 9508946
    Abstract: An organic light emitting diode display includes: a substrate; a thin film transistor provided on the substrate; a first electrode connected to the thin film transistor; an organic emission layer provided on the first electrode; an interlayer provided on the organic emission layer; an electron auxiliary layer provided on the interlayer and including an electron injection layer (EIL) and an electron transport layer (ETL); and a second electrode provided on the electron auxiliary layer, wherein the interlayer is made by mixing a material of the electron auxiliary layer.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: November 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ha-Jin Song, Sang-Woo Pyo, Byeong-Wook Yoo, Ji-Young Kwon, Bum-Suk Lee, Ji-Myoung Ye, Ji-Hwan Yoon
  • Carbon nanotube field effect transistor
    Patent number: 9502659
    Abstract: A nanotube-based flexible field effect transistor and its method of manufacture is provided. The field effect transistor according to the invention comprises at least two contact electrodes, respectively drain and source electrodes, an electrical conduction zone connected to the contact electrodes, said zone comprising a plurality of single-wall carbon nanotubes that are substantially aligned, a gate electrode for controlling the electric current circulating in said zone and a flexible substrate on which the contact and gate electrodes are deposited. The nanotube density in the conduction zone is strictly greater than 10 nanotubes per micrometer.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: November 22, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-Philippe Bourgoin, Marcelo Goffman, Vincent Derycke, Nicolas Chimot
  • Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers
    Patent number: 9502363
    Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael B. Vincent, Trung Q. Duong, Zhiwei Gong, Scott M. Hayes, Alan J. Magnus, Douglas G. Mitchell, Eduard J. Pabst, Jason R. Wright, Weng F. Yap