Abstract: A method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at each end of FET channels. Source/drain regions adjacent to each channel placeholder extend into and fill the undercut. The channel placeholder is opened to expose channel surface under each channel placeholder. Source/drain extensions are formed under each channel placeholder, adjacent to each source/drain region. After removing the channel placeholders metal gates are formed over each said FET channel.

Abstract: A method of manufacturing a mask includes aligning a mask substrate comprising a thin film at a processing position, forming a coating layer comprising a cleaning solution material on a first surface of the mask substrate, forming a deposition pattern on a second surface of the mask substrate, and removing the coating layer from the mask substrate comprising the deposition pattern.

Abstract: A light-emitting diode (LED) includes a first type semiconductor layer, a second type semiconductor layer, a current controlling structure, a first electrode, and a second electrode. The second type semiconductor layer is joined with the first type semiconductor layer. The current controlling structure is joined with the first type semiconductor layer, and the current controlling structure has at least one current-injecting zone therein. The first electrode is electrically coupled with the first type semiconductor layer through the current-injecting zone of the current controlling structure. The second electrode is electrically coupled with the second type semiconductor layer.

Abstract: An organic light-emitting display device, a method of manufacturing the same, and a donor substrate and a donor substrate set used to manufacture the organic light-emitting display device.

Abstract: A device includes a source region, a drain region, and a semiconductor channel connecting the source region to the drain region. The semiconductor channel includes a source-side channel portion adjoining the source region, wherein the source-side channel portion has a first bandgap, and a drain-side channel portion adjoining the drain region. The drain-side channel portion has a second bandgap different from the first bandgap.

Abstract: An electronic circuit structure comprising a substrate, a dielectric layer on top of the substrate and comprising a cavity having side-walls, a manganese or manganese nitride layer covering the side-walls, and a self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract: A method for producing a display device includes forming a resin film on a substrate, forming a plurality of light emitting elements above the resin film, forming a plurality of first grooves in a surface of the resin film, the plurality of first grooves enclosing the plurality of light emitting elements individually in a multiple-fold manner, cutting the substrate at a position overlapping any one of the plurality of first grooves other than the first groove closest to one of the plurality of light emitting elements, and peeling off the substrate from the resin layer.

Abstract: Heterostructure field-effect transistor (HFET) having a channel layer, a barrier layer disposed on the channel layer, and a gate, source and drain electrodes disposed on the barrier layer, respectively, and corresponding fabrication methods are disclosed. The drain electrode includes a p-type semiconductor patterned structure and a raised drain section, the drain electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface together with a side surface of p-type semiconductor patterned structure and a bottom surface together with a side surface of raised drain section, the ohmic contact is formed between another surface of raised drain section and barrier layer, the raised drain section partially surrounding the p-type semiconductor patterned structure, and a bandgap of the channel layer is less than a bandgap of the barrier layer.

Abstract: An AMOLED display backboard, a display device and a manufacturing method of an AMOLED display backboard are provided. In the AMOLED display backboard, the number of VDD lines (601) is less than that of sub-pixels in one row, thus reducing area occupied by the VDD lines (601), lessening occupation of VDD lines (601) on the area of circuit board, while realizing connection of circuit input terminals (603) of respective sub-pixels and VDD lines (601) by the VDD connecting line (602).

Abstract: An optical device has a gallium and nitrogen containing substrate including a surface region and a strain control region, the strain control region being configured to maintain a quantum well region within a predetermined strain state. The device also has a plurality of quantum well regions overlying the strain control region.

Abstract: The embodiment of the present invention provides a pixel structure, pixel unit structure, display panel and display apparatus, which is used to increase the electrical-optical efficiency of the display apparatus. The pixel structure includes an active matrix driving circuit, also includes at least two light emitting devices connected in series which are connected to the active matrix driving circuit, the light emitting devices compose the light emitting device group, and the active matrix driving circuit drives the light emitting devices to emit light.

Abstract: A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

Abstract: A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer.

Abstract: A first semiconductor substrate having at least one integrated semiconductor device is provided. A lift-off layer is formed on a main surface of the first semiconductor substrate. The lift-off layer is patterned so as to form openings in the lift-off layer that are arranged on either side of a first portion of the lift-off layer. The first substrate is connected together with a second substrate by an interconnect structure to form an assembly with the main surface of the first semiconductor substrate being exposed. Exposed surfaces of the assembly are coated with a parylene coating, with a first portion of the parylene coating being supported by the first portion of the lift-off layer. The first portion of the parylene coating is selectively removed using a lift-off technique that removes the first portion of the lift-off layer. The lift-off technique is performed after connecting the first substrate and second substrates together.

Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dice coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract: A back-illuminated sensor chip is disclosed, which includes one or more pixel areas each including a plurality of pixels located in a plane and arranged in a matrix. Each pixel area includes: a central portion consisting of a plurality of first pixels located in vicinity of a center of the pixel area; and a peripheral portion surrounding the central portion and consisting of the other pixels in the pixel area than the first pixels. The plurality of first pixels have a first height in a vertical direction perpendicular to the plane, and the pixels in the peripheral portion have a second height in the vertical direction that is greater than the first height so that the peripheral portion protrudes outward beyond the central portion and is thus located nearer to a light source during imaging than the central portion. As a result, light sensibility of the peripheral portion is increased.

Abstract: Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.

Abstract: In an aspect, an organic light emitting diode device including a first electrode, a second electrode facing the first electrode, and an emission layer positioned between the first electrode and second electrode, wherein the first electrode includes samarium (Sm) is provided.