Patents Examined by Laura Menz
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Patent number: 9735265Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.Type: GrantFiled: November 10, 2016Date of Patent: August 15, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer Pendharkar, Seetharaman Sridhar
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Patent number: 9728470Abstract: In an embodiment, a method for evaluating a surface of a semiconductor substrate includes directing an incident light beam having multiple wavelengths at a position of a layer having a surface profile configured to form an optical diffraction grating, the layer including a Group III nitride, detecting a reflected beam, reflected from the position, and obtaining a spectrum of reflected intensity as a function of wavelength, the spectrum being representative of the surface profile of the position of the layer from which the beam is reflected, comparing the spectrum obtained from the detected beam with one or more reference spectra stored in memory, and estimating at least one parameter of the surface profile.Type: GrantFiled: May 10, 2016Date of Patent: August 8, 2017Assignee: Infineon Technologies Austria AGInventors: Franz Heider, Bernhard Brunner, Clemens Ostermaier
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Patent number: 9722112Abstract: Methods and semiconductor materials produced by such methods that are suitable for use in photovoltaic cells, solar cells fabricated with such methods, and solar panels composed thereof. Such methods include a wet-chemical synthesis method capable of producing a Group I-III-VI2 semiconductor material by forming a solution containing an organic solvent, at least one Group I precursor of at least one Group I element, and at least one Group III precursor of at least one Group III element. The Group I precursor is present in the solution in an amount of less than 120% of a stoichiometric ratio of the Group I element in the Group I-III-VI2 semiconductor material, and the Group III precursor is present in the solution in an amount of greater than 55% of a stoichiometric ratio of the Group III element in the Group I-III-VI2 semiconductor material.Type: GrantFiled: March 12, 2014Date of Patent: August 1, 2017Inventor: Suneel Girish Joglekar
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Patent number: 9722025Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: GrantFiled: January 5, 2016Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 9716226Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.Type: GrantFiled: December 1, 2016Date of Patent: July 25, 2017Assignee: Intel CorporationInventors: F. Daniel Gealy, Andrea Gotti, Davide Colombo, Kuo-Wei Chang
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Patent number: 9711512Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.Type: GrantFiled: October 30, 2016Date of Patent: July 18, 2017Assignee: Renesas Electronics CorporationInventor: Koji Nii
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Patent number: 9703036Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.Type: GrantFiled: February 11, 2016Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Zhong-Xiang He, Qizhi Liu, Ronald G. Meunier, Steven M. Shank
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Patent number: 9704829Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.Type: GrantFiled: October 14, 2015Date of Patent: July 11, 2017Assignee: Win Semiconductor Corp.Inventors: Chang-Hwang Hua, Chih-Hsien Lin
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Patent number: 9698119Abstract: A method of forming a structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint. More specifically, in this structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.Type: GrantFiled: May 19, 2016Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Hirokazu Noma, Yasumitsu Orii, Kazushige Toriyama
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Patent number: 9698289Abstract: A method for detaching a self-supporting layer of silicon of crystalline orientation <100>, particularly with the aim of applications in the field of photovoltaics, wherein the method includes the steps of: a) Implanting ionic species in a substrate made of silicon having a crystalline orientation <100> so as to create an embrittlement plane in the substrate, delimiting on both sides a self-supporting layer and a negative of the substrate, and b) Applying a heat treatment to the substrate implanted at step a) with a temperature ramp greater than 30° C./s so as to detach the self-supporting layer of silicon.Type: GrantFiled: July 1, 2013Date of Patent: July 4, 2017Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Carole Braley, Frédéric Mazen
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Patent number: 9690153Abstract: An electro-optical device includes a first light shielding film; a transistor element formed on the first light shielding film to overlap the first light shielding film; a second light shielding film formed on the transistor element to overlap the transistor element and electrically connected to an input terminal of the transistor element; a transparent conductive film extended toward an upper layer side of the second light shielding film in an opening region, through which light penetrates, of the display region; a dielectric film formed on the transparent conductive film in the opening region; and a transparent pixel electrode formed on the dielectric film in the opening region, constituting a storage capacitor together with the transparent conductive film and the dielectric film, and having a transparent pixel electrode which is electrically connected to the transistor element.Type: GrantFiled: November 25, 2015Date of Patent: June 27, 2017Assignee: SEIKO EPSON CORPORATIONInventor: Takunori Iki
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Patent number: 9691695Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.Type: GrantFiled: August 31, 2015Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Pen Guo, Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin
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Patent number: 9691842Abstract: A semiconductor device includes first semiconductor regions of a first conductivity type spaced apart from each other and second semiconductor regions of a second conductivity type between adjacent first semiconductor regions. At least one second semiconductor region includes a void having at least one outer surface with a crystal plane orientation of (100). A third semiconductor region of the second conductivity type is on each second semiconductor region and a fourth semiconductor region of the first conductivity type is on the third semiconductor region. A gate electrode on is disposed on each first semiconductor region to be adjacent to a third semiconductor region via a gate insulation layer.Type: GrantFiled: August 26, 2015Date of Patent: June 27, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Sato, Tomoyuki Sakuma, Noboru Yokoyama, Shizue Matsuda
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Patent number: 9680013Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.Type: GrantFiled: September 5, 2013Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
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Patent number: 9679946Abstract: The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors).Type: GrantFiled: August 25, 2015Date of Patent: June 13, 2017Assignee: HGST, Inc.Inventor: Daniel R. Shepard
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Patent number: 9679934Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.Type: GrantFiled: December 20, 2016Date of Patent: June 13, 2017Assignee: Powerchip Technology CorporationInventors: Tse-Wei Chung, Tsung-Hui Chou, Hsu-Ting Chang
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Patent number: 9679945Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, a resistance change layer provided between the first and second conductive layers, a third conductive layer, a fourth conductive layer and a first intermediate layer. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is arranged with the second conductive layer in a direction crossing the first direction. The fourth conductive layer is arranged with the third conductive layer in the first direction. The fourth conductive layer is electrically connected with the third conductive layer. The first intermediate layer is provided between a portion of the third conductive layer and a portion of the fourth conductive layer.Type: GrantFiled: March 11, 2016Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Yusuke Kobayashi
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Patent number: 9673228Abstract: A display panel is provided, which includes a substrate and a first metal layer on the substrate. The first metal layer includes a gate electrode and a gate line connecting to the gate electrode. A first insulation layer is disposed on the first metal layer. A planarization layer is disposed on the first insulation layer. An opening, overlapping the gate electrode, is defined by sidewalls of the planarization layer and a surface of the first insulation layer. An active layer is disposed on the opening and the planarization layer. A second metal layer is disposed on the semiconductor layer, and includes a source electrode contacting the active layer and a data line connecting to the source electrode. The planarization layer and the first insulation layer are disposed between the data line and the gate line.Type: GrantFiled: January 20, 2016Date of Patent: June 6, 2017Assignee: INNOLUX CORPORATIONInventor: Kuan-Feng Lee
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Patent number: 9673224Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.Type: GrantFiled: October 16, 2014Date of Patent: June 6, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Shuhei Nagatsuka, Tatsuya Onuki, Yutaka Shionoiri, Kiyoshi Kato, Hidekazu Miyairi
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Patent number: 9673280Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.Type: GrantFiled: March 6, 2007Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu
