Abstract: A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer.

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

Abstract: A back-side illumination image capturing apparatus includes a semiconductor substrate having a first surface for receiving incident light and a second surface located on the opposite side as the first surface, and including a photoelectric conversion portion, and a gate electrode disposed above the second surface. The apparatus further includes a first insulating layer disposed above the second surface of the semiconductor substrate, an interlayer insulation film disposed on the first insulating layer, a contact plug connected to the gate electrode, and a light-cutting portion for cutting light, of the incident light, that has passed through the photoelectric conversion portion. The light-cutting portion passes through at least part of the interlayer insulation film. The first insulating layer is located between the light-cutting portion and the semiconductor substrate.

Abstract: An integrated circuit layout includes a first metal line, a second metal line, at least one first conductive via and a first conductive segment. The first metal line is formed along a first direction. The at least one first conductive via is disposed over the first metal line. The second metal line is disposed over at least one first conductive via and is in parallel with the first metal line. The first conductive segment is formed on one end of the second metal line.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer on an underlying layer, a first trench formed in the first insulating layer, and a first graphene layer provided in the first trench. The first trench comprises a bottom surface on the underlying and two side surfaces joined to the bottom surface, formed into a U-shape. The first graphene layer has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a depression in a central portion. Portions of the graphene sheets located in an edge of the first graphene layer are each extended upward, which is in a direction opposite to the bottom surface.

Abstract: The invention relates to an electroluminescent device (10) comprising a layer system with a substrate (40) and on top of the substrate (40) a substrate electrode (20), a counter electrode (30) and an electroluminescent layer stack with at least one organic electroluminescent layer (50) arranged between the substrate electrode (20) and the counter electrode (30), characterized in that at least one optical transparent outcoupling body (71) is provided on top of the substrate electrode (20) to increase the outcoupling of light generated by the at least one organic electroluminescent layer (50) at least partly covering the optical transparent outcoupling body (71). The invention further relates to a method to manufacture such a device.

Abstract: A method of manufacturing a cantilever structure includes providing a semiconductor substrate, forming a recess in the semiconductor substrate, forming a sacrificial layer in the recess, forming a cantilever structure layer on the semiconductor substrate and the sacrificial layer, performing an etching process to remove a portion of the cantilever structure layer until a surface of the sacrificial layer is exposed to form a cantilever structure and an opening, and removing a portion of the sacrificial layer to form a void below the cantilever structure so that the cantilever structure is suspended in the void. The cantilever structure thus formed has good morphological properties to ensure that the cantilever structure is free of residues at the bottom and has excellent suspension even if the width of the cantilever structure is relatively large.

Abstract: A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even if a single crystal semiconductor substrate including crystal defects is used. A first oxide film is formed on a single crystal semiconductor substrate; the first oxide film is removed; a surface of the single crystal semiconductor substrate from which the first oxide film is removed is irradiated with laser light; a second oxide film is formed on the single crystal semiconductor substrate; an embrittled region is formed in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with ions through the second oxide film; bonding the second oxide film and the semiconductor substrate so as to face each other; and the single crystal semiconductor substrate is separated at the embrittled region by heat treatment to obtain a single crystal semiconductor layer bonded to the semiconductor substrate.

Abstract: The present inversion provides an organic display device comprising at least infrared display pixel, the infrared display pixel includes a transparent substrate which is deposited with a first electrode layer, an infrared organic light emitting layer and a second electrode layer thereon, and the infrared organic light emitting layer is filled with an infrared light emitting material. The present invention can allow the organic display device to carry out large area of infrared display; and the present invention uses the flexible transparent substrate, so as to conveniently use and carry the organic display device.

Abstract: In an aspect, an organic light emitting diode device including a first electrode, a second electrode facing the first electrode, and an emission layer positioned between the first electrode and second electrode, wherein the first electrode includes samarium (Sm) is provided.

Abstract: An organic light emitting display device includes a plurality of first sub-pixels arranged adjacent to each other along a first direction, each of the first sub-pixels includes a first emission region configured to emit light of a first color and a first transmission region configured to transmit external light, the first emission regions of at least two of the first sub-pixels are adjacent to each other; and a plurality of second sub-pixels arranged adjacent to each other along the first direction and adjacent to corresponding ones of the plurality of first sub-pixels along a second direction crossing the first direction, each of the plurality of second sub-pixels includes a second emission region configured to emit light of a second color and a second transmission region configured to transmit external light, the second emission regions of at least two of the sub-pixels are adjacent to each other.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: The invention relates to an electronic component including a leadframe, composed of a platform, and possibly at least one electrical connecting piece, wherein at least one electronic member is located on the platform, and including a housing that encloses the electronic member and the platform, wherein at least one support region is provided to support the platform during the fabrication process for the housing, and wherein at least a section of the at least one support region projects from the housing.

Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: In an electronic component including two substrates at least one of which is transparent, an organic member arranged between these substrates, and a bonding portion located onto respective outer circumferential portions of the two substrates, this bonding portion includes a low-melting glass and filler particles. The low-melting glass includes vanadium oxide. The filler particles include a low thermally-expandable material, and an oxide containing a bivalent transition metal as a constituent element. The oxide is dispersed in the low thermally-expandable material, and the low thermally-expandable material has a thermal expansion coefficient of 5×10?7/° C. or less in a temperature range from 30 to 250° C. This invention makes it possible to heat the filler particles by irradiation with a laser to give the electronic component which is a component having a highly reliable bonding portion.

Abstract: A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.

Abstract: A flexible solar module strand manufactured by a method including providing a first conveyor track for applying flexible solar cells; guiding the first conveyor track around two or more deflecting means; providing individual flexible solar cells; applying the individual solar cells to the first conveyor track; deflecting the first conveyor track by guiding the first conveyor track over a first one of the deflecting means; separating the first conveyor track from the at least one deflected solar cell strip in such a manner that the solar cells are released, with their respective first or second sides facing the first conveyor track, from the first conveyor track; and applying the at least one deflected solar cell strip to a first film web in such a manner that the solar cells are oriented, with their respective first or second sides separated from the first conveyor track, away from the first film web.

Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.