Abstract: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region.

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

Abstract: In an electro-optical device, a relay electrode (first electrode) includes a conduction section that overlaps the projection portion of an inter-layer insulation film, and the conduction section is exposed from the surface (flat surface) of the inter-layer insulation film. An insulation film which has a film thickness thinner than the height of the projection portion is formed on the surface (flat surface) of the inter-layer insulation film, and a pixel electrode is electrically conducted to the conduction section through the opening of the insulation film. In this case, since the opening is shallow, a large uneven part is hardly generated on the surface of the pixel electrode.

Abstract: An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.

Abstract: Provided is an imaging element including: a light receiving element 20; and a stacked structure body 130 that is placed on a light incident side of the light receiving element 20 and in which a semiconductor layer 131 and a nanocarbon film 132 to which a prescribed electric potential is applied are stacked from the light receiving element side. The semiconductor layer 131 is made of a wide gap semiconductor with an electron affinity of 3.5 eV or more, or is made of a semiconductor with a band gap of 2.0 eV or more and an electron affinity of 3.5 eV or more.

Abstract: A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region.

Abstract: A method of sealing a workpiece comprising forming an inorganic film over a surface of a first substrate, arranging a workpiece to be protected between the first substrate and a second substrate wherein the inorganic film is in contact with the second substrate; and sealing the workpiece between the first and second substrates as a function of the composition of impurities in the first or second substrates and as a function of the composition of the inorganic film by locally heating the inorganic film with a predetermined laser radiation wavelength. The inorganic film, the first substrate, or the second substrate can be transmissive at approximately 420 nm to approximately 750 nm.

Abstract: A system and method for manufacturing a semiconductor device are provided. In an embodiment a first semiconductor device and a second semiconductor device are encapsulated with an encapsulant. A dielectric layer is formed over the encapsulant, the first semiconductor device, and the second semiconductor device. The dielectric layer is planarized in order to reset the planarity of the dielectric layer.

Abstract: Embodiments of the present disclosure are directed towards metallization of a fluorocarbon-based dielectric material for interconnect applications. In one embodiment, an apparatus includes a semiconductor substrate, a device layer disposed on the semiconductor substrate, the device layer including one or more transistor devices, and an interconnect layer disposed on the device layer, the interconnect layer comprising a fluorocarbon-based dielectric material, where x represents a stoichiometric quantity of fluorine relative to carbon in the dielectric material, and one or more interconnect structures configured to route electrical signals to or from the one or more transistor devices, the one or more interconnect structures comprising cobalt (Co), or ruthenium (Ru), or combinations thereof. Other embodiments may be described and/or claimed.

Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.

Abstract: Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (LED) device includes a heat sink, an LED die thermally coupled to the heat sink, and a phosphor spaced apart from the LED die. The LED device also includes a heat conduction path in direct contact with both the phosphor and the heat sink. The heat conduction path is configured to conduct heat from the phosphor to the heat sink.

Abstract: An array substrate and a display panel are provided. The array substrate includes a non-display region and a display region including a plurality of pixel unit rows arranged in a first direction and extended in a second direction. Each pixel unit row includes at least one first-pixel unit having a first width in the first direction and a second width in the second direction. At least one pixel unit row includes at least one second-pixel unit having a third width in the first direction and a fourth width in the second direction, and the at least one second-pixel unit is disposed at one end or both ends of the pixel unit row. The second width is larger than or equal to the fourth width.

Abstract: Disclosed herein are sealed devices comprising a first substrate, a second substrate, an inorganic film between the first and second substrates, and at least one weld region comprising a bond between the first and second substrates. The weld region can comprise a chemical composition different from that of the inorganic film and the first or second substrates. The sealed devices may further comprise a stress region encompassing at least the weld region, in which a portion of the device is under a greater stress than the remaining portion of the device. Also disclosed herein are display and electronic components comprising such sealed devices.

Abstract: Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.

Abstract: A transistor cell region of a semiconductor device includes transistor cells that are electrically connected to a first load electrode. An idle region includes a gate wiring structure that is electrically connected to gate electrodes of the transistor cells. A transition region, which is disposed between the transistor cell region and the idle region, includes at least one sensor cell that is electrically connected to a sense electrode. The at least one sensor cell is configured to convey a unipolar current during an on state of the transistor cells.

Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Abstract: An organic light emitting diode display includes a substrate, a transistor on the substrate, a reflecting electrode connected to the transistor, a color filter on the reflecting electrode, a first electrode on the color filter and electrically connected to the reflecting electrode, a pixel definition layer on the color filter and having an opening exposing the first electrode, a white emission layer in the opening and a second electrode on the white emission layer.

Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.

Abstract: A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05.

Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.