Abstract: A method includes growing a graphene layer on a metal layer, intercalating a first material between the metal layer and the graphene layer by heating the first material at a first pressure and a first temperature, and intercalating a second material between the metal layer and the graphene layer by heating the second material at a second pressure different from the first pressure and a second temperature different from the first temperature. Accordingly, the first material and the second material are chemically bonded to each other to form an insulating layer, and the insulating layer may be between the metal layer and the graphene layer.

Abstract: A semiconductor memory device according to an embodiment comprises: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; and a memory cell disposed at an intersection of the first wiring line and the second wiring line, the memory cell including a first film whose resistance changes electrically, a second film having conductivity, and a third film having an insulating property which are stacked sequentially in a third direction that intersects the first and second directions.

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

Abstract: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias.

Abstract: A semiconductor device is operated for sensing incident light and includes a substrate, a device layer, a semiconductor layer and a color filter layer. The device layer is disposed on the substrate and includes light-sensing regions. The semiconductor layer overlies the device layer and has a first surface and a second surface opposite to the first surface. The first surface is adjacent to the device layer. The semiconductor layer includes microstructures on the second surface. The color filter layer is disposed on the second surface of the semiconductor layer.

Abstract: An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die.

Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A miniaturized semiconductor device includes an oxide semiconductor, the first conductor, the second conductor, the third conductor, the first insulator, and the second insulator. The first conductor is embedded in a region between the second conductor and the third conductor with the first insulator positioned between the first conductor and the region.

Abstract: An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is formed in the dielectric layer, in which the dielectric layer includes a damaged layer adjacent to the opening. Next, a dielectric protective layer is formed in the opening, a metal layer is formed in the opening, and the damaged layer and the dielectric protective layer are removed.

Abstract: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.

Abstract: A light emitting device improves light extraction efficiency and may be individually driven in a light emitting device package and/or a light unit. The light emitting device may include first and second light emitting structures. The light emitting structure may include a first conductive first semiconductor layer, a first active layer under the first conductive first semiconductor layer, and a second conductive second semiconductor under the first active layer. The second light emitting structure may include a first conductive third semiconductor layer, a second active layer under the first conductive third semiconductor layer, and a second conductive fourth semiconductor layer under the second active layer.

Abstract: A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad.

Abstract: Topological insulators can be utilized in a new type of infrared photodetector that is intrinsically sensitive to the polarization of incident light and static magnetic fields. The detector isolates single topological insulator surfaces and allows light collection and exposure to static magnetic fields. The wavelength range of interest is between 750 nm and about 100 microns. This detector eliminates the need for external polarization selective optics. Polarization sensitive infrared photodetectors are useful for optoelectronics applications, such as light detection in environments with low visibility in the visible wavelength regime.

Abstract: A method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at each end of FET channels. Source/drain regions adjacent to each channel placeholder extend into and fill the undercut. The channel placeholder is opened to expose channel surface under each channel placeholder. Source/drain extensions are formed under each channel placeholder, adjacent to each source/drain region. After removing the channel placeholders metal gates are formed over each said FET channel.

Abstract: A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N+-type emitter region and p++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates. P+-type region covers an end portion on lower side of junction interface between n+-type emitter region and p++-type contact region. Formation of trench gate structure is such that n+-type emitter region is selectively formed at predetermined intervals in the first direction in the mesa portion by first ion implantation. P+-type region is formed less deeply than n+-type emitter region in the entire mesa portion by second ion implantation. The p++-type contact region is selectively formed inside the p+-type region by third ion implantation. N+-type emitter region and p++-type contact region are diffused and brought into contact.

Abstract: In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel. The photodiodes in the pixel are arranged in a direction orthogonal to the longitudinal direction of the pixel allay section.

Abstract: The present invention generally relates to a system and method for the precise measurement of acceleration, movement, and other forces imparted on a body or object. Specifically, the invention relates to a system and method for measuring head accelerations in helmeted activities including, but not limited to, football, ice hockey, and lacrosse. Certain embodiments of the invention may include a wireless link to a remote recording station with near real-time data analysis and reporting of force and kinetics measured by the system.

Abstract: A pixel structure of a liquid crystal display panel and a manufacturing method thereof are provided, the pixel structure adopts a tri-gate frame, and one thin film transistor and one storage capacitor are simultaneously formed during the manufacturing process. The storage capacitor has a first via and a second via to connect a first capacitor layer and a second capacitor layer of the storage capacitor. A main storage portion of the storage capacitor further includes a lower portion of a common line, so as to substantially increase the capacity of the storage capacitor and reduce a feed through effect produced by the parasitic capacitor of the liquid crystal display panel, and to improve the display quality of the panel.

Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.

Abstract: An LED light-emitting element having reduced the occurrence of illuminance unevenness is provided. A light-emitting element comprising a substrate, an LED element mounted on the substrate, a phosphor resin arranged on the substrate so as to seal the LED element and having an emission surface from which light based on light emitted from the LED element is emitted, a reflective resin arranged around the phosphor resin; and a reflecting frame having an opening and at least part of which is arranged on the reflective resin, wherein the reflective resin is arranged directly under the reflecting frame and on the side surface of the phosphor resin, the ratio of the area of the emission surface to the area of an inside area of the reflecting frame is set to 80% or higher, and in the inside area of the reflecting frame, the reflective resin is exposed around the emission surface.