Abstract: An asynchronous FIFO (firstin, firstout) device suitable for use as a buffer comprises a stack having a plurality of sections. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX (multiplexer) having a first input connected to receive a logic signal indicative of the condition of the preceding subassembly, a second input connected to receive a logic signal indicative of the condition of the following subassembly and an output connected to the associated storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.

Abstract: To lock use of shared information to itself in a multiprocessor system (100) having two independently and asynchronously operating processors (101, 111) whose main store units (102, 112) duplicate each other's contents, a processor must cause an atomic read-modify-write (RMW) operation to be executed on a semaphore in the duplicated main store units of both processors. To properly order execution of multiple such RMW operations, arbiters (106, 116) of system buses (105, 115) of the two processors communicate over an interarbiter channel (121). The arbiter of a source processor that wishes to perform an RMW operation notifies the other processor's arbiter over the interarbiter channel. Simultaneous attempts at notification by both arbiters are resolved in favor of one of them that is designated the master. The notifying arbiter prevents its processor from performing another RMW operation until the one RMW operation has completed thereon, but permits other operations to proceed normally.

Abstract: A system for checking a spelling of an English word which stores a plurality of English words in several groups. Every word in each group can have a common suffix and is stored without the suffix. The system searches whether or not an input word exists in the dictionary memory and judges next whether or not an input word has one of the suffixes by which the words in the dictionary memory are classified. If the input word has one of the suffixes, the system searches a de-suffixed form of the input word within the group corresponding to the suffix. The search result and input words are displayed on a cathode ray tube.

Abstract: An interface circuit controls the unloading of a host computer system onto a peripheral processor unit. The interface circuit has a normal mode of operation which is independent of the host computer. During the normal mode, the peripheral unit processes data previously supplied by the host computer. The interface device has a trap I/O mode of operation in which information flows between the host computer and the peripheral unit. The trap I/O mode is initiated by a range of instruction addresses from the peripheral unit. In one embodiment, any instruction address less than a predetermined critical value initiates the trap I/O mode. The host computer acknowledges the trap I/O mode, and executes the instruction at the host level to advance the peripheral process. In the trap I/O mode, the peripheral processor operates simultaneous with and independently of the peripheral unit to permit unloading of the host computer.

Abstract: Security of communications in a packet-switched data communications system is enhanced by introducing terminal and host security devices into the system in communicative relationship with a terminal and a host processor, respectively. In response to a user-initiated data entry at the terminal, the terminal security device generates an initial data packet indicative of user authorization or not, but which is unsuited for processing by the addressed processor, ahead of additional data packets containing user-entered message data to be processed by the addressed processor. The host security device intercepts and processes the initial data packet and, if user authorization is indicated therein, replaces it with an artificial data packet solely to render the additional packets amenable to processing by the addressed processor and thereby to establish a communications session between user terminal and processor-associated database to which access was requested.

Abstract: The system includes a dictionary memory for storing a plurality of English words which are classified into two groups consisting of noun words and non-noun words, respectively; search circuitry for searching whether or not an inputted word exists in the dictionary memory; and suffix judgment circuitry for judging whether or not an inputted word has a possessive suffix. If the inputted word has one of the possessive suffixes, the group of noun words in the dictionary memory is searched to find the coincident word data to the de-suffixed input word. An output display displays the input word and the search result.

Abstract: An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a translate map gate array generates an address to the translate RAM in response to mapped and remapped instructions being fetched from the instruction buffer. The map gate array looks at an operation code included in the instructions and determines if remapping is required. If so, an address is generated including a constant providing a block of specific addresses and a variable providing a specific address within the block. The mapped instruction includes a seven bit operation code field and, in response to a mapped instruction being fetched, all of the seven bits are mapped directly to the translate RAM address.

Abstract: An apparatus for checking a spelling of an input English word and for storing a new English word is provided, including an input device for receiving a word, an electronic dictionary memory consisting essentially of a first dictionary in which pre-installed English words are stored and a second dictionary for storing new English words and a search device for searching an input word through the first and the second dictionary. A store is also provided for storing a new input word that has not been found in either the first or the second dictionary into the second dictionary which includes an address memory in which an address of the second dictionary for starting the word searching is stored. A writing device is provided for writing the new input word at just before the address stored in the address memory, and a change is provided for changing the address in the address memory to the head address of the written word.

Abstract: A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented.

Abstract: This pipeline processor has an ALU, an accumulator register, a first data bus connected through a first switch circuit to output terminals of the accumulator register, and a second data bus connected to input terminals of the accumulator register through a second switch circuit. Data on the first data base is processed by the ALU, and supplied through a third switch circuit to the second data bus. First to third switch circuits respectively receive first to third control signals generated at a predetermined timing for controlling the data transfer by the signal generator of an execution control circuit. The execution control circuit is further provided with signal generator for generating a fourth control signal which renders the second switch circuit conductive during the precharge period of the first and second data buses. The third and fourth control signals are supplied through an OR gate to the second switch circuit.

Abstract: An Laser Doppler Velocimeter multiplexer interface (20) includes an event pulse synchronizer (162), which synchronizes data pulses from events A, B and C. Clock control (164) is connected to receive timing information on the data pulses from the synchronizer (162). Displays (24, 26, 28) are connected to receive clock signals from the clock control (164) for indicating a data rate for each of the measured events A, B and C. Display (30) is connected to receive clock signals from the clock control (164) to indicate a coincidence rate between data pulses for any selected combination of the measured events A, B and C. A multiplexer (156) receives the data pulses from the events A, B and C and rate data from the clock control (164). Multiplexer (156) has output (180) for supplying the data pulses and rate data to a single input of a data processing system.

Abstract: An address space, referred to herein as Moby space, may be defined having an address range greatly exceeding the direct addressing range of a particular computer, whereby each address in Moby space may be unique. Ranges of Moby space are swapped into and out of local memory space of the computer in question by processes referred to as reconciliation and dereconciliation. These processes are accomplished by maintaining in the computer, data structures which associate, typically on a per page or per section (multiple page) basis, each local page or section with its current Moby page or section. In addition to this address association and conversion, information being swapped must be scanned to separate the pointers from data and to appropriately convert pointers, but not data, as required during the swap.

Abstract: For a computer system having peripheral devices coupled to a common bus through interface devices transmitting and receiving messages containing an address code matching a stored address code, a dynamic address assignment system stores a unique address code in each interface device following system startup. On system start up each interface device stores a type number and an adjustable serial number, type numbers for peripheral devices of the same type being identical while serial numbers for all peripheral devices of the same type are adjusted to different values. A master controller transmits to all peripheral devices a series of universally addressed count commands. Each interface device counts the count commands and, when the count reaches a poll number determined by the unique combination of stored type and serial numbers, requests and obtains a unique address code from the host computer.

Abstract: Synchronous apparatus capable of a variety of operational states responds to a sequence of digital control words, each specifying a desired state and persistence time of the state. The control words are furnished to the apparatus from a self-clocked FIFO in accord with the persistence code. A selected sub-sequence of digital control words in ROM is placed in an auxiliary FIFO upon detection of a corresponding token in the main sequence and control is passed to the auxiliary FIFO to furnish the sub-sequence to the apparatus. At the conclusion of the sub-sequence control is returned to the main FIFO and the main sequence is resumed.

Abstract: A method for improving the quality of code generated by a compiler or assembler, for a target machine that has short and long forms of some of its instructions with the short forms executing faster or occupying less space. The method first determines which bits of the result of each computational instruction are significant, by a backwards pass over the program that is similar to liveness analysis. Then the significant bits thus computed are used to guide the code selection process to select the most efficient instruction that computes the correct result in all the significant bit positions.

Abstract: In automatic development of the higher hierarchic logic into the lower hierarchic logic in a hierarchic logic designing, identification codes are beforehand assigned to logic components of the higher hierarchic logic, and the identification codes are also assigned to the lower hierarchic logic data when developing the higher hierarchic logic into the lower hierarchic logic in order to establish correspondences between the higher and lower hierarchic logic, thereby allowing a higher-speed logic compare operation with respect to a design change on the higher or lower hierarchic logic and enabling the automatic update of the lower hierarchic logic by use of the higher hierarchic logic as the master.

Abstract: A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices.

Abstract: An input/output control system has a control unit including a first controller connected between a channel and a data buffer for controlling the transfer of data therebetween and a second controller connected between the data buffer and a plurality of input/output devices for controlling the transfer of data therebetween. A start action of the input/output device is effected in an off-line mode from the control unit. The amount of data stored in the data buffer is checked each time the transfer of data occurs between the channel and the data buffer. In the case of a read processing, when the amount of data stored in the data buffer becomes less than a first predetermined value, data is transferred for preload from the input/output devices to the data buffer. In the case of a write processing, when the amount of data stored in the data buffer exceeds a second predetermined value, data is transferred for after-write from the data buffer to the input/output devices.

Abstract: The invention relates to vector registers (VRs) which have associated therewith a vector status register (VSR) that includes VR status information in the form of vector in-use and change bits for saving and restoring (the contents of) the VRs. When the vector in-use bit for a VR is zero, the saving and subsequent restoring of the VR is eliminated because the VR is known to contain all zeros. This reduces program switching time. The vector change bit for a VR serves to reduce switching time still further by permitting the saving of a VR to be eliminated when its vector in-use bit is one but the vector change bit is zero. Although such a VR is in use, its content has not been changed since the last restore from the same save area in storage. The previously saved information is still valid. The vector change bits do not affect the restoring of vector registers and, therefore, do not reduce the restore time.

Abstract: Automated spelling correction converts, by prescribed linguistic procedures, each word to be corrected to a skeleton, and compares that skeleton with a data base of skeletons derived by identical linguistic procedures from a dictionary of correctly spelled words. In the event of a match between the two skeletal terms, the correctly spelled word (or words) associated with the matched skeleton is presented for replacement of the misspelled word. In the event the comparison does not yield a correct match, the skeletal form of the misspelled word is repeatedly modified and each modified form is compared with the data base of skeletons.